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United States Patent | 5,523,976 |
Okazawa ,   et al. | June 4, 1996 |
A plurality of semiconductor memory cells are arranged in the form of a matrix and capable of electrically erasing and re-programming. Each of word lines is provided commonly to the memory cells in each row of the matrix and commonly connected to the gates of these memory cells, and each of bit lines is provided commonly to the memory cells in each column of the matrix and commonly connected to the drains of these memory cells. Each of common source lines is commonly connected to the sources of the memory cells in each pair of adjacent rows of the matrix. A memory cell group in a predetermined row or row pair of the matrix is operative as a redundant memory cell group for replacement of the other group.
Inventors: | Okazawa; Takeshi (Tokyo, JP); Saitoh; Kenji (Tokyo, JP) |
Assignee: | NEC Corporation (Tokyo, JP) |
Appl. No.: | 388453 |
Filed: | February 14, 1995 |
Feb 16, 1994[JP] | 6-042006 |
Current U.S. Class: | 365/200; 365/185.09; 365/218; 714/710 |
Intern'l Class: | G11C 007/00 |
Field of Search: | 365/200,185,218 371/10.1,10.2,10.3 |
5033024 | Jul., 1991 | O'Connell et al. | 365/200. |
5185718 | Feb., 1993 | Rinerson et al. | 365/185. |
5195057 | Mar., 1993 | Kasa et al. | 365/200. |
5422843 | Jun., 1995 | Yamada | 365/185. |
5426608 | Jun., 1995 | Hagashitani | 365/200. |
Foreign Patent Documents | |||
2-5470 | Jan., 1990 | JP. |