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United States Patent | 5,506,874 |
Izzard ,   et al. | April 9, 1996 |
A phase detector 10 is disclosed herein. A clock signal CLK (OR I), a marker signal MARK (or Q) and a data signal D are provided. The data signal may comprise a periodic clock signal. Sampler circuitry 50 receives the clock signal CLK, the marker signal MARK and the data signal D and generates a sampled clock signal and a sampled marker signal. Sign modifier circuitry 52 then receives the sampled clock signal and sampled marker signal and generates first and second command signals. Select circuitry 54 receiving these command signals selects a valid command signal based upon the data signal.
Inventors: | Izzard; Martin J. (Dallas, TX); Scott; David B. (Plano, TX) |
Assignee: | Texas Instruments Incorporated (Dallas, TX) |
Appl. No.: | 146680 |
Filed: | November 1, 1993 |
Current U.S. Class: | 375/340; 327/2; 375/376 |
Intern'l Class: | H03D 001/00 |
Field of Search: | 375/81,120,94,110 328/109,133 307/510,511 |
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4535459 | Aug., 1985 | Hogge, Jr. | 375/80. |
4773085 | Sep., 1988 | Cordell | 375/120. |
4789996 | Dec., 1988 | Butcher | 375/120. |
4975660 | Dec., 1990 | Svenson | 375/120. |
5027085 | Jun., 1991 | DeVito | 375/120. |
5056120 | Oct., 1991 | Taniguchi et al. | 307/510. |
5120602 | Jun., 1992 | Lee et al. | 307/511. |
5233636 | Aug., 1993 | Lee et al. | 375/120. |
Pottbacker et al., "A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gb/s", IEEE Journal of Solid-State Circuits, vol. 27, No. 12, Dec. 1992, pp. 1747-1751. Lee et al., "A 155-MHz Clock Recovery Delay- and Phase-Locked Loop", IEEE Journal of Solid-State Circuits, vol. 27, No. 12, Dec. 1992, pp. 1736-1746. |