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United States Patent | 5,343,502 |
Sato | August 30, 1994 |
An amplitude detection circuit generates an amplitude signal by detecting an amplitude of a received signal modulated by .pi./4 shift QPSK , and a first shift register and all amplitude difference detection circuit calculate an amplitude difference signal from the amplitude signal. Then, a second shift register and a calculation circuit calculate an amplitude difference accumulation signal from the amplitude difference signal, and a decision circuit generates a preset signal by deciding a sampling time from the amplitude difference accumulation signal and a preset signal. A counter divides a master clock signal by the preset signal, thereby generating a symbol clock signal.
Inventors: | Sato; Toshifumi (Tokyo, JP) |
Assignee: | NEC Corporation (Tokyo, JP) |
Appl. No.: | 982950 |
Filed: | November 30, 1992 |
Nov 29, 1991[JP] | 3-316942 |
Current U.S. Class: | 375/354; 375/332; 375/371 |
Intern'l Class: | H04L 007/027 |
Field of Search: | 375/106,111,110,54,83,85,86,118,119 329/304 |
Re34206 | Mar., 1993 | Sayar | 375/118. |
3599103 | Aug., 1971 | LeGarde | 375/119. |
4128828 | Dec., 1978 | Samejima et al. | 375/85. |
4672447 | Jun., 1987 | Moring et al. | 375/111. |
4941155 | Jul., 1990 | Chuang et al. | 375/106. |
5122758 | Jun., 1992 | Tomita | 375/84. |
5235622 | Aug., 1993 | Yoshida | 375/106. |
5243630 | Sep., 1993 | Rhebergen | 375/106. |
Foreign Patent Documents | |||
3-188736 | Aug., 1991 | JP. |