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United States Patent | 5,324,974 |
Liao | June 28, 1994 |
A method is described for fabricating a lightly doped drain MOSFET integrated circuit device. The method begins by forming a pattern of gate electrode structures upon a semiconductor substrate which structures each includes a gate oxide, a polysilicon layer and a refractory metal silicide. A thin silicon nitride layer is formed over each of the structures and the exposed surfaces therebetween of the substrate. A pattern of lightly doped regions in the substrate is formed by ion implantation using the polycide gate structures as the mask. A dielectric spacer structure is formed upon the sidewalls of each of the polycide gate structures and over the adjacent portions of the substrate. A pattern of heavily doped regions in the substrate is formed by ion implantation using the polycide structures with spacer structures as the mask to produce the lightly doped drain source/drain structures of an MOSFET device. The integrated circuit device is completed by forming a passivation layer over the structures described and appropriate electrical connecting structures thereover to electrically connect the gate electrode structures and source/drain elements.
Inventors: | Liao; I-Chi (Tao-Yuan Hsien, TW) |
Assignee: | Industrial Technology Research Institute (Hsinchu, TW) |
Appl. No.: | 046781 |
Filed: | April 14, 1993 |
Current U.S. Class: | 257/344; 257/408; 257/413; 257/640; 257/649; 257/900; 257/E21.641 |
Intern'l Class: | H01L 029/68; H01L 029/78 |
Field of Search: | 257/412,413,408,900,639,640,344 |
4690730 | Sep., 1987 | Tang et al. | 156/643. |
4935380 | Jun., 1990 | Okumura | 257/408. |
5030585 | Jul., 1991 | Gonzalez et al. | 257/408. |
Foreign Patent Documents | |||
195607A | Sep., 1986 | EP | 257/408. |
59-159544 | Sep., 1984 | JP | 257/412. |
61-81664 | Apr., 1986 | JP | 257/412. |
6358971 | Mar., 1988 | JP | 257/344. |