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United States Patent | 5,283,870 |
Joyce ,   et al. | February 1, 1994 |
A multiprocessor system includes a number of system processors which tightly couple to a system bus to share a main or system memory and a number of on-board memory processors which also are tightly coupled to the system bus. Each processor has a high performance microprocessor which tightly couples to an on-board or local memory through the microprocessor's local bus. System memory is accessible using a memory lock protocol while the local memory is accessible through a bus lock protocol. Each on-board memory processor includes a lock mechanism which enables the processing of memory lock commands directed to its local memory received via the system bus from any other processor and for issuing memory lock commands to system memory.
Inventors: | Joyce; Thomas F. (Westford, MA); Keeley; James W. (Nashua, NH) |
Assignee: | Bull HN Information Systems Inc. (Billerica, MA) |
Appl. No.: | 771296 |
Filed: | October 4, 1991 |
Current U.S. Class: | 711/152; 711/155 |
Intern'l Class: | G06F 013/14 |
Field of Search: | 395/800,200,375 364/241.8,242.91,252.4,927.96,927.97 |
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