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United States Patent | 5,280,608 |
Beaverson ,   et al. | January 18, 1994 |
A system and method for testing a computing system by introducing stall cycles at an arbiter that controls access to a bus that is commonly used by the CPU and I/O devices for stressing the computing system with regard to the latency and bandwidth.
Inventors: | Beaverson; Authur J. (Maynard, MA); Hunt; Thomas E. (Brookline, NH); Lidington; Gary P. (Wayland, MA) |
Assignee: | Digital Equipment Corporation (Maynard, MA) |
Appl. No.: | 724379 |
Filed: | June 28, 1991 |
Current U.S. Class: | 714/34; 714/745 |
Intern'l Class: | G01R 031/318 |
Field of Search: | 371/16.1,18,28 395/575,425,275,325,550 340/825.5 370/85.2 364/240.5,271.6 |
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