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United States Patent | 5,276,818 |
Okazawa ,   et al. | January 4, 1994 |
A bus system for an information processing system in which data transfer among plurality of modules is controlled on a common bus. In response to a bus use request from a module, a command is issued for aborting data transfer being performed by another module having a lower priority. The module which is transferring the data responds to the abort command by issuing a signal indicating that a word being transferred is the final word. The data is transferred between a master and a slave through an address bus having a same width as the data in synchronism with a clock supplied from a bus controller.
Inventors: | Okazawa; Koichi (Tokyo, JP); Aotsu; Hiroaki (Yokohama, JP); Kawaguchi; Hitoshi (Yokohama, JP); Jikihara; Masami (Ebina, JP); Kobayashi; Kazushi (Ebina, JP); Kimura; Koichi (Yokohama, JP); Mochida; Tetsuya (Yokohama, JP) |
Assignee: | Hitachi, Ltd. (Tokyo, JP) |
Appl. No.: | 512810 |
Filed: | April 20, 1990 |
Apr 24, 1989[JP] | 1-101621 | |
Dec 25, 1989[JP] | 1-332716 |
Current U.S. Class: | 710/114 |
Intern'l Class: | G06F 013/00 |
Field of Search: | 364/200,900,DIG. 1,DIG. 2 395/325,725 |
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4807116 | Feb., 1989 | Katzman et al. | 364/200. |
4959775 | Sep., 1990 | Yonekura | 364/200. |
5047921 | Sep., 1991 | Kinter et al. | 364/200. |
IEEE Standard Backplane Bus Specification for Multiprocessor Architecture: Futurebus, ANSI/IEEE Std. 896.1-1987, pp. 73-119. IEEE Standard for a Simple 32 bit Backplane Bus Nubus. ANSI/IEEE Std. 1196-1987, 21-62. |