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United States Patent | 5,253,353 |
Mogul | October 12, 1993 |
A data processing system (10) includes a CPU (12) connected to a direct-mapped cache (14) by address bus (16) and data bus (18). The cache (14) includes a first-level cache (20) connected to a second-level cache (22) by address bus (24) and data bus (26). The second-level cache (22) of the cache (14) is connected to address bus (28) and data bus (30) by address bus (32) and data bus (34). The address and data busses (28) and (30) are connected to memory (36) and I/O device (41) by address bus (40), data bus (42), address bus (44) and data bus (46), respectively. In the system (10), I/O interface (38) decodes physical memory addresses and responds to addresses in specific ranges using first and second addresses alternately, which are chosen to collide in the data cache (14). I/O software alternates between the two addresses instead of alternating between a device register address and a reserved-region address as in prior art systems.
Inventors: | Mogul; Jeffrey C. (Menlo Park, CA) |
Assignee: | Digital Equipment Corporation (Maynard, MA) |
Appl. No.: | 459445 |
Filed: | January 2, 1990 |
Current U.S. Class: | 711/122 |
Intern'l Class: | G06F 012/08; G06F 013/00 |
Field of Search: | 364/200 MS File,900 MS File 395/400 MS File,425 MS File |
4802085 | Jan., 1989 | Levy et al. | 395/375. |
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