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United States Patent | 5,245,208 |
Eimori | September 14, 1993 |
A semiconductor device includes a first neutral impurity layer formed to a predetermined depth from a surface of a semiconductor substrate in a channel region that is interposed between source/drain regions and located below a gate electrode, and a second neutral impurity layer having a higher concentration than that of the first neutral impurity layer and formed to surround lower portions of the source/drain regions except for the channel region. Scattering of neutral impurities in the first neutral impurity layer suppresses generation of hot carriers, and the second neutral impurity layer suppresses diffusion of impurities in the source/drain regions in thermal processing. The second neutral impurity layer is formed by implanting neutral impurities obliquely after formation of the gate electrode.
Inventors: | Eimori; Takahisa (Hyogo, JP) |
Assignee: | Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP) |
Appl. No.: | 867741 |
Filed: | April 13, 1992 |
Apr 22, 1991[JP] | 3-090834 |
Current U.S. Class: | 257/344; 257/408; 257/607; 257/616; 257/E21.335; 257/E21.345; 257/E29.04; 257/E29.063; 257/E29.269 |
Intern'l Class: | H01L 029/78 |
Field of Search: | 357/23.4 257/344,408,616,607,900 |
4835112 | May., 1989 | Pfiester et al. | 257/607. |
5134447 | Jul., 1992 | Ng et al. | 357/23. |
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