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United States Patent | 5,226,152 |
Klug ,   et al. | July 6, 1993 |
N redundant processors operating in functional lockstep synchronization for maintaining system integrity. Comparison and synchronization logic are connected between N processors in redundant configuration and peripheral devices. The comparison and synchronization logic act to insure that the redundant processors are performing the same read/write operations. Calculation or processing not requiring access to peripherals may take place in an asynchronous manner. Processors are halted from performing further operations until all appropriate read or write operations are synchronized. The processors are then allowed to proceed. An overall watchdog timer provides for detecting an error condition for non-responsive or lead responding processors.
Inventors: | Klug; Keith M. (Mesa, AZ); Tugenberg; Steven R. (Scottsdale, AZ) |
Assignee: | Motorola, Inc. (Schaumburg, IL) |
Appl. No.: | 623843 |
Filed: | December 7, 1990 |
Current U.S. Class: | 714/12; 714/9 |
Intern'l Class: | G06F 011/00 |
Field of Search: | 371/68.3,36 364/269,269.1,270.7 375/575 |
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