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United States Patent | 5,179,358 |
Martin | January 12, 1993 |
An electronic circuit (100) includes a load stage circuit (116) having at least one FET (118 and 120). The load stage circuit (116) includes an adjustment terminal responsive to an adjustment voltage for controlling the load resistance of the FET (118 and 120). The electronic circuit (100) also includes a bias current generator (124) for generating a bias current. A current steering circuit (122) controls the amount of bias current supplied to the load stage circuit (116). The electronic circuit (100) also includes a plurality of output terminals (112 and 114) for providing an output which is responsive to voltages applied at input terminals (104, 106 and 108) of the current steering circuit (122). Circuit (100) alllows for the adjustment of the bias current to the circuit in order to achieve optimum power dissipation over changing operating conditions.
Inventors: | Martin; Frederick L. (Gainsville, FL) |
Assignee: | Motorola, Inc. (Schaumburg, IL) |
Appl. No.: | 845573 |
Filed: | March 4, 1992 |
Current U.S. Class: | 331/1A; 323/350; 327/544; 331/8; 331/25; 331/186 |
Intern'l Class: | H03L 007/18; H03K 021/00 |
Field of Search: | 331/1 A,8,15,25,186 307/296.1,296.3,296.4,296.5,296.7 323/349,350,351 |
3958135 | May., 1976 | Rosenthal | 307/296. |
4999519 | Mar., 1991 | Kitsukawa et al. | 307/296. |
IEEE Journal of "Solid State Circuits", Oct. 1990, vol. 25, No. 5, pp. No. 1136-1140. |