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United States Patent |
5,175,816
|
Kimura
,   et al.
|
December 29, 1992
|
Method and apparatus for bit operational process
Abstract
A bit operation processor having a first address operation unit for
updating the address of data in units of a byte or multiple bytes for
performing operation in units of a byte or multiple bytes, a second
address operation unit for updating the address of data in units of a bit
or multiple bits, an address control means operating on the first address
operation unit to advance the address in response to the result of address
advancement by the second address operation unit, and means for fetching
byte-wide data for operation as addressed by the first address operation
unit, whereby operation between data of any number of bits at any
positions in byte blocks is controlled simply and fast.
Inventors:
|
Kimura; Koichi (Yokohama, JP);
Ogura; Toshihiko (Ebina, JP);
Aotsu; Hiroaki (Yokohama, JP);
Urabe; Kiichiro (Hadano, JP)
|
Assignee:
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Hitachi, Ltd. (Tokyo, JP)
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Appl. No.:
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641064 |
Filed:
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January 14, 1991 |
Foreign Application Priority Data
| Oct 05, 1984[JP] | 59-208257 |
| Oct 05, 1984[JP] | 59-208267 |
Current U.S. Class: |
345/561; 345/501; 345/565; 345/566 |
Intern'l Class: |
G06F 015/20 |
Field of Search: |
364/518,521
340/703,724,747,750,798-800
395/162,164-166
|
References Cited
U.S. Patent Documents
4251864 | Feb., 1981 | Kindell et al. | 364/200.
|
4363091 | Dec., 1982 | Pohlman, III et al. | 364/200.
|
4435792 | Mar., 1984 | Bechtolsheim | 365/230.
|
4449184 | May., 1984 | Pohlman, III et al. | 364/200.
|
4862150 | Aug., 1989 | Katsura et al. | 340/703.
|
Other References
Hitachi 16-Bit Microcomputer HD63484 Aerte Advanced CRT Controller 4th
edition Mar. 1988, pp. 98, 204, 205.
|
Primary Examiner: Herndon; Heather R.
Attorney, Agent or Firm: Antonelli, Terry, Stout & Kraus
Parent Case Text
This is a continuation of application Ser. No. 779,794, filed Sep. 24,
1985, now U.S. Pat. No. 5,034,900.
Claims
We claim:
1. A bit operation processing apparatus for processing data comprising:
memory means having a plurality of addresses for storing N bit data in word
unit at each of said addresses;
a central processing unit for generating a data processing command for
processing M bit source data and M bit destination data said M being an
integer number;
address register means for respectively storing start addresses of said M
bit source data and said M bit destination data, each of said start
addresses designating an arbitrary position of said N-bit data;
read-access means for generating said addresses corresponding to said N bit
data respectively including at least a part of said M bit source data
indicated by said start address of said M bit source data and at least a
part of said M bit destination data indicated by said start address of
said M bit destination data, read-accessing said N bit data of said
generated addresses and generating a consecutive one of said addresses
when said M bit source data or said M bit destination data reaches beyond
a word boundary of said N bit data; and
bit operation means for operating on said M bit source data and said M bit
destination data.
2. A bit operation processing apparatus according to claim 1, wherein:
said bit operation means executes logic operations on said M bit source
data and said M bit destination data.
3. A bit operation processing apparatus according to claim 2, wherein:
said bit operation means executes a transfer of said M bit source data to
corresponding bit positions of said M bit destination data as one of said
logic operations.
4. A bit operation processing apparatus according to claim 1, wherein:
said bit operation means executes arithmetic operations on said M bit
source data and said M bit destination data.
5. A bit operation processing apparatus according to claim 1, wherein:
said N bit data is image data.
6. A bit operation processing apparatus according to claim 5, wherein:
said image data is pixel data.
7. A bit operation processing apparatus according to claim 1, further
comprising:
width register means having a length of L bits for storing binary data
corresponding to M bits.
8. A bit operation processing apparatus according to claim 7, further
comprising:
means for obtaining new start addresses of said M bit source data and said
M bit destination data by using said start addresses stored in said
address register means and said binary data stored in said width register
means.
9. A data processing apparatus for processing data, comprising:
memory means for storing N bit data words at a plurality of memory
positions;
memory interface means for transferring addresses corresponding to said
memory positions to read/write said N bit data words from/to said memory
means;
a central processing unit for generating a data processing command for
processing M bit source data and M bit destination data, said M being an
integer number;
position register means for storing a start bit position of said M bit
source data and a start bit position of said M bit destination data at a
start of a process indicated by said processing command, said start bit
position being an arbitrary bit position of one of said N bit data words;
memory access means for generating said addresses corresponding to said N
bit data words respectively including at least a part of said M bit source
data and at least a part of said M bit destination data indicated by said
start bit positions, read-accessing said N bit data words stored at said
generated addresses and generating said addresses corresponding to a
consecutive one of the N bit data words when another part of said M bit
source data or said M bit destination data exists beyond a word boundary
of said N bit data words; and
bit operation means for operation on said M bit source data and said M bit
destination data read-accessed from said memory means in response to said
processing command.
10. A data processing apparatus according to claim 9, wherein:
said bit operation means executes logic operations on said M bit source
data and said M bit destination data.
11. A data processing apparatus according to claim 9, wherein:
said bit operations means executes arithmetic operations on said M bit
source data and said M bit destination data.
12. A data processing apparatus according to claim 11, wherein:
said bit operation means executes a transfer of said M bit source data to
corresponding bit positions of said M bit destination data as one of said
logic operations.
13. A data processing apparatus according to claim 9, wherein:
said N bit data words are image data words.
14. A data processing apparatus according to claim 9, further comprising:
width register means having a length of L bits a length of for storing
binary data corresponding to M bits.
15. A data processing apparatus according to claim 14, further comprising:
means for updating said start bit positions stored in said position
register means with said binary data stored in said width register means
after the operation of said bit operation means.
16. An image data processing apparatus for processing image data to be
displayed in display means, comprising:
image memory means for storing image data at a plurality of address
positions;
memory interface means for transferring addresses corresponding to said
address positions to read/write N bit image data from/to said memory
means, said N being an integer number;
central processing means for generating an image data processing command
for processing M bit source image data and M bit destination image data,
said M being an integer number; and
bit operation processing means for processing said M bit source image data
and said M bit destination image data in response to said image data
processing command;
wherein said bit operation processing means includes:
bit register means for storing a start bit position of said M bit source
image data and a start bit position of said M bit destination image data
at a start of a process indicated by said image data processing command,
said start bit position being an arbitrary bit position of one of said N
bit image data,
memory access means for generating said addresses corresponding to said N
bit data respectively including at least a part of said M bit source image
data and at least a part of said M bit destination image data indicated by
said start bit positions, read-accessing said N bit image data stored on
generated said addresses, and generating said addresses corresponding to a
consecutive one of the N bit data when said M bit source image data or
said M bit destination image data straddles a word boundary of said N bit
data, and
bit operation means for operating on said M bit source image data and said
M bit destination image data read-accessed from said memory means in
response to said image data processing command.
17. An image data processing apparatus according to claim 16, wherein said
bit operation processing means further includes:
data register means for storing said M bit source image data and said M bit
destination image data read-accessed by said memory access means and to be
operated on by said bit operation means.
18. An image data processing apparatus according to claim 17, wherein said
bit operation means executes logic operations on said M bit source image
data and said M bit destination image data stored in said bit register
means.
19. An image data processing apparatus according to claim 18, wherein said
bit operation means executes a transfer of said M bit source image data to
corresponding bit positions of said M bit destination image data as one of
said logic operations.
20. An image data processing apparatus according to claim 16, wherein said
image memory means is a bit-map memory.
21. A bit operation processing method in an operation processing system,
which includes a memory having a plurality of memory addresses for storing
an N bit data word at each of the memory addresses and a central
processing unit (CPU), to process source data and destination data stored
in the memory, the method comprising the steps of:
(a) indicating start addresses and field lengths of M bit data
corresponding to the source data and the destination data in bit units in
response to a data processing command from the CPU, said M being an
integer, and each of said start addresses indicating an arbitrary bit
position of an N bit data word;
(b) generating the memory addresses of the N bit data words respectively
including at least a part of said M bit data corresponding to the source
data and the destination data;
(c) read-accessing the N bit data words from the memory in accordance with
the memory addresses;
(d) generating the memory address corresponding to a consecutive one of the
N bit data words when the source data or the destination data straddles a
word boundary of said N bit data words and;
(e) operating on the source data and the destination data.
22. A bit operation processing method according to claim 21, the method
further including the steps of:
(f) storing the operation result of said operating step (e) in the memory
address of the N bit data word corresponding to the destination data.
23. A bit operation processing method according to claim 21, wherein:
the operation of said operating step (e) is a logic operation between the
source data and the destination data.
24. A bit operation processing method according to claim 21, wherein:
the operation of said operating step (e) is an arithmetic operation between
the source data and the destination data.
25. A bit operation processing method according to claim 24, wherein:
said logic operation is an operation to transfer said M bit data
corresponding to the source data to corresponding bit positions of said M
bit data corresponding to the destination data.
26. A bit operation processing method according to claim 21, wherein:
the source data and the destination data are image data.
27. A bit operation processing method according to claim 26, wherein:
said image data are pixel data.
28. A bit operation processing method according to claim 21, the method
further including the step of:
(f) obtaining new start addresses of said M bit data respectively
corresponding to the source data and the destination data by using said
start addresses and said field lengths.
29. A bit operation processing method according to claim 28, the method
further including the step of:
(g) renewing said memory addresses of the N bit data words respectively
including said M bit data corresponding to the source data and the
destination data in accordance with the result of the step (f).
30. A bit operation processing method according to claim 21, wherein:
said memory addresses are word addresses.
31. A bit operation processing method for processing image data stored in a
memory, comprising:
(a) a first step of incrementing addresses of the image data in units of an
integral number of words independent from each other;
(b) a second step of incrementing addresses of the image data in units of
an integral number of bits independent from each other;
(c) a third step of causing said first step to increment said addresses
based on the result of incrementing addresses in said second step; and
(d) a fourth step of reading the image data in word units from locations in
the memory designated by said addresses produced in said first step, and
performing operations to the image data read from the memory.
32. An operation processing apparatus having a memory for processing image
data stored in the memory comprising:
(a) first means for incrementing first addresses for addressing stored
operand data and operating data in units of an integral number of words
independent from each other;
(b) second means for incrementing second addresses for addressing said
image data to be processed in units of an integral number of bits
independent from each other;
(c) third means for controlling said second means to increment said second
addresses and for controlling said first means to increment said first
addresses based on the result of said incrementing by said second
addresses by said second means; and
(d) fourth means for fetching the image data in units of a word at
locations of said first addresses produced by said first means, and for
performing operations to said image data fetched from the memory.
33. A bit operational processing apparatus having a memory storing N bit
fixed-length data word in each of a plurality of memory address positions
thereof, comprising:
data processing means for processing source and destination data, said
source and destination data being M bit variable length data,
respectively,
size register means for storing size data of said M bit variable length
data;
address register means for storing start bit positions of said source and
destination data, each of said start bit positions indicating an arbitrary
position of said N bit fixed-length data word; and
memory access means for read/write accessing said source and destination
data from/to the memory, generating memory address positions corresponding
to the N bit fixed-length data word including said source and destination
data indicated by said address register means to provide the N bit
fixed-length data word including said source and destination data from the
memory to said data processing means and generating a memory address
position corresponding to a consecutive one of the N bit fixed-length data
word when said source or destination data straddles a word boundary of the
N bit fixed-length data word.
34. A bit operation processing apparatus according to claim 33, wherein
said address register means includes an upper part for storing a word
address indicating one of the N bit fixed-length data words stored in the
memory and a lower part for storing a bit address indicating a start bit
position of said M bit variable length data in the N bit fixed-length data
word indicated by said word address of said upper part, and wherein said
memory access means generates the memory address position in accordance
with said word address of said upper part.
35. A bit operational processing apparatus according to claim 34, wherein
said memory access means generates the memory address position of the N
bit fixed-length data word including a part of said M bit variable length
data to be processed by said data processing means in accordance with said
size data, said word address, and said bit address.
36. A bit operational processing apparatus according to claim 35, wherein
the memory accesses to the N bit fixed-length data words including said M
bit variable length data to be processed by said data processing means are
executed in accordance with the sum of said size data and said bit
address.
37. A bit operational processing apparatus according to claim 36, wherein a
start bit position of a next one of said M bit variable length data to be
processed by said data processing means in the N bit fixed-length data
word is determined by the sum of said size data and said bit address.
38. A bit operational processing apparatus according to claim 34, wherein
said data processing means includes a means for bit-aligning a bit
boundary designated by said bit address.
39. A bit operational processing apparatus according to claim 34, wherein
said data processing means includes a data mask means for masking at least
one bit except said M bit variable length data to be processed in the N
bit fixed-length data word.
40. A bit operational processing apparatus according to claim 33, wherein
said bit operation means executes logic operations on said source and
destination data.
41. A bit operational processing apparatus according to claim 40, wherein
said bit operation means executes a transfer of said source data to
corresponding bit positions of said destination data as one of said logic
operations.
42. A bit operation processing apparatus according to claim 33, wherein
said bit operation means executes arithmetic operations on said source and
destination data.
43. A bit operational processing apparatus according to claim 33, wherein
the N bit fixed-length data word is image data.
44. A bit operational processing apparatus according to claim 33, wherein
the N bit fixed-length data word is pixel data.
45. An operational processing apparatus comprising:
memory means having word boundaries for storing word data at each of a
plurality of addresses thereof;
memory access means for accessing said word data stored in said memory
means by generating said addresses corresponding to said word data
including at least a part of source and destination data, at least one of
said source and destination data having a width which straddles one of
said word boundaries; and
data processing means for processing said source and destination data
accessed by said memory access means.
46. An operational processing apparatus according to claim 45, further
comprising:
a plurality of first data registers for temporarily storing said word data
including said source data to be processed; and
a plurality of second data registers for temporarily storing said word data
including said destination data to be processed.
47. An operational processing apparatus according to claim 45, wherein:
said source data straddles one of said word boundaries, said data
processing means changes said destination data to said source data, and
said memory access means accesses said memory means to write therein said
word data including said changed destination data.
48. An operational processing apparatus according to claim 45, wherein:
said destination data straddles one of said word boundaries, said data
processing means changes said destination data to said source data, and
said memory access means accesses said memory means to write therein said
word data including said changed destination data.
49. An operational processing apparatus according to claim 45, wherein said
word boundaries are fixed-length N bit word boundaries and said word data
are fixed-length N bit ordered data.
50. An operational processing apparatus according to claim 45, wherein said
width is an arbitrary width of M bits.
51. An operation processing apparatus comprising:
memory means having word boundaries for storing word data at each of a
plurality of addresses thereof; and
data processing means for processing source and destination data each
having an arbitrary bit width, at least one of said source and destination
data having an arbitrary bit width which straddles one of said word
boundaries from an arbitrary bit position of said word data.
52. An operational processing apparatus according to claim 51, further
comprising:
a plurality of first data registers for temporarily storing said word data
including said source data; and
a plurality of second data registers for temporarily storing said word data
including said destination data.
53. An operational processing apparatus according to claim 51, wherein said
word boundaries are fixed-length N bit word boundaries and said word data
are fixed-length N bit word data.
54. An operational processing apparatus according to claim 51, wherein said
bit width is an arbitrary bit width of M bits.
55. A bit operational processing apparatus comprising:
memory means, having a plurality of addresses An where n is an integer and
fixed-length N bit word boundaries, for storing fixed-length N bit word
data at each of said addresses An;
memory access means for accessing said fixed-length N bit word data from
said memory means by generating said addresses An-1 and An corresponding
to said fixed-length N bit word data including at least a part of an
arbitrary M bit width data straddling one of said fixed-length N bit word
boundaries;
a set of first and second data registers for temporarily storing said
fixed-length N bit word data of said addresses An-1 and An, respectively;
and
data processing means for processing said arbitrary M bit width data
temporarily stored in said set of first and second data registers;
wherein said memory access means generates a new address An, accesses said
fixed-length N bit word data corresponding to said new address an in said
memory means, stores said fixed-length N bit word data stored in said
second data register to said first data register and stores said
fixed-length N bit word data corresponding to said new address
56. An operational processing method for operating on word data by data
processing means, said method comprising the steps of:
storing said word data at each of a plurality of addresses in memory means
having word boundaries;
accessing said word data stored in said memory means by generating said
addresses corresponding to said word data, said word data including at
least a part of source and destination data, at least one of said source
and destination data having a width which straddles one of said word
boundaries; and
processing said source and destination data accessed by said accessing step
in said data processing means.
57. An operational processing method according to claim 56, wherein said
word boundaries are fixed-length N bit word boundaries and said word data
are fixed-length N bit word data.
58. An operational processing method according to claim 56, wherein said
width is an arbitrary width of M bits.
59. An operational processing method comprising the steps of:
storing word data in memory means having word boundaries; and
processing source and destination data each having an arbitrary bit width,
at least one of said source and destination data having an arbitrary bit
width which straddles one of said boundaries from an arbitrary bit
position of said word data.
60. An operational processing method according to claim 59, wherein said
word boundaries are fixed-length N bit word boundaries and said word data
are fixed-length N bit word data.
61. An operational processing method according to claim 59, wherein said
bit width is an arbitrary bit width of M bits.
62. An operational processing apparatus comprising:
bit map memory means having word boundaries for storing N bit fixed length
word data at each of a plurality of addresses thereof;
memory access means for accessing said N bit fixed length word data by
generating said addresses corresponding to said N bit fixed length word
data including at least a part of source and destination data, said source
and destination data respectively belonging to source and destination
rectangular areas, each of said rectangular areas is stored from an
arbitrary bit position of said N bit fixed length word data in said bit
map memory means, and at least one of said source and destination data
having an arbitrary M bit width which straddles one of said word
boundaries, and
data processing means for processing said source and destination data
accessed by said memory access means.
63. An operational processing apparatus according to claim 62, wherein:
said data processing means executes a bit block transfer of said source
data to corresponding bit positions of said destination data.
64. An operational processing apparatus according to claim 62, wherein:
said N bit fixed length word data is image data.
65. An operational processing apparatus according to claim 62, wherein:
said N bit fixed length word data is pixel data.
66. An operational processing apparatus according to claim 62, wherein said
data processing means executes logic operations on said source and
destination data.
67. An operational processing apparatus according to claim 66, wherein said
data processing means executes a transfer of said source data to
corresponding bit positions of said destination data as one of said logic
operations.
68. An operational processing apparatus according to claim 62, wherein said
data processing means executes arithmetic operations on said source and
destination data.
69. An operational processing apparatus according to claim 62, wherein said
data processing means executes a bit-alignment of said source and
destination data.
70. An operational processing apparatus according to claim 62, wherein said
data processing means executes a data mask of at least one bit except said
source or destination data to be processed in said N bit fixed length word
data.
Description
BACKGROUND OF THE INVENTION
The present invention relates to a digital processing system and,
particularly, to a method and apparatus for bit operational process
suitably used in an image processing system having a bit-map display.
At first, we will provide a description of an example of image processing
intended by the present invention, as shown in FIG. 1; and then, we will
describe certain problems which result when this image processing is
implemented on a conventional system, with reference to FIG. 3. Referring
to FIG. 1, reference symbol M1 denotes a memory area storing image data in
1-to-1 correspondence to a CRT (Cathode Ray Tube) screen, M2 denotes a
memory area storing image data to be added to the image data in M1,
X.sub.A and X.sub.B denote partial areas in M1 and M2, respectively, for
which image data processing takes place, W.sub.A0, W.sub.A1, W.sub.A2,
W.sub.B0 and W.sub.B1 denote boundaries of data words having a word length
of 16 bits, for example, R.sub.0 through R.sub.m represent raster lines
for the partial areas X.sub.A and X.sub.B, na and nb represent
displacements of the leading edges of the areas X.sub.A and X.sub.B from
the word boundaries W.sub.A0 and W.sub.B0, respectively, A.sub. 0 through
A.sub.n and B.sub.0 through B.sub.n represent addresses of word data in
the areas X.sub.A and X.sub.B, and MFY denotes a modification unit for
implementing the alignment and processing for the areas X.sub.A and
X.sub.B having different starting bit positions na and nb.
Since the currently available processing unit such as a microprocessor
deals with data and makes access to the memory in units of a word or a
byte, the memory areas M1 and M2 shown in FIG. 1 have a word or byte
structure. However, in image processing, a partial screen area to be
processed is specified from the outside of the system without regard to
the word boundary as shown by areas X.sub.A and X.sub.B in FIG. 1. On this
account, image processing for combining the partial areas X.sub.A and
W.sub.B needs a modification unit MFY with the following three processing
functions.
(1) Rearrangement of word data so that processing can take place on a
word-wide basis between data for areas X.sub.A and X.sub.B with different
starting bit positions na and nb.
(2) Separation of data section from word-wide data e.g., na bits, in each
of addresses A.sub.0, A.sub.3, . . . , A.sub.n-2 so that it is retained
unchanged in the processing.
(3) Data processing in any specific number of bits (bit width) so that
monochrome display is implemented using one bit per pixel while color
display uses a plurality of bits per pixel (generally four bits per
pixel).
The operation of the modification unit having these functions will be
described in connection with FIG. 2. Throughout the following description,
it is assumed that the image data memory is addressed in units of a word.
FIG. 2 shows a 2-word- register SRC(A) and SRC(B) for storing data read out
of the processing area X.sub.B, a 2-word register DST(A) and DST(B) for
storing data read out of the processing area X.sub.A, and a 2-word
register MRG(A) and MRG(B) for storing the result of processing for the
contents of the registers SRC(A, B) and DST(A, B). The modification unit
MFY performs rotation of the register SRC(A, B), i.e., shift of SRC
content with bit 0 of SRC(A) linked with bit F of SRC(B), depending on the
values of SN (i.e., nb) and DN (i.e., na) representing the starting bit
positions of the processing areas X.sub.A and X.sub.B, as follows.
(a) For SN>DN: Rotate the SRC content left by a number of bits of SN-DN.
(b) For SN<DN: Rotate the SRC content right by a number of bits of DN-SN.
(c) For SN=DN: No operation.
In this way, bit addresses nb(SN) and na(DN) are used to align the
operation starting bit position.
Consequently, the starting bit position of the SRC content is adjusted to
that of the DST content. The bit width of processing, WN, is set in
advance, and the remaining portion of data is left unchanged. Although in
FIG. 2 the result register MRG(A, B) is provided independently of DST(A,
B), they may be arranged in common. After the subsequent processing, the
original bit position of the SRC content is restored automatically.
Next, the 4-bit image processing for the areas X.sub.A and X.sub.B by the
modification unit MFY will be described in connection with FIGS. 3, 4, 5
and 6. The process shown in FIG. 3 includes step S1 of setting the
starting address A.sub.0 for the processing area X.sub.A, step S2 of
setting DN to the starting bit position (address) na, step S3 of setting
the starting address B.sub.0 for the processing area X.sub.B, step S4 of
setting SN to the starting bit position (address) nb, step S5 of the
process implemented by the modification unit MFY mentioned above, steps
S6-S9 for the area X.sub.B for obtaining the next bit address (S6),
setting the next SN (S7), incrementing the address in word units (S8) and
reading next word data (S9), and steps S10-S14 for the area X.sub.B for
obtaining the next bit address (S10), setting the next DN (S11), writing
the result of process in the register MRG(A) (S12), incrementing the
address in word units (S13) and reading the next word data (S14). The
process further includes decision steps SB1 and SB2, which implement the
following operations.
(I) Decision step SB1
This step tests as to whether the next SN address of SRC resulting from the
steps S6 and S7 as in the following expression (1) reaches beyond the word
boundary as in the following expression (2), and controls the sequence to
fetch the next word data when the condition (2) is met.
SN=SN+WN (1)
SN.gtoreq.(10).sub.HEX ( 2)
(II) Decision step SB2
This step tests as to whether the next DN address of DST resulting from the
steps S10 and S11 reaches beyond the word boundary as in the following
expression (3), and controls the sequence to write data in the register
MRG(A) to the area X.sub.A when the condition (3) is met, which indicates
the end of operation at the current word boundary.
DN.gtoreq.(10).sub.HEX ( 3)
The above operations for one raster (R0) will be described in more detail
in connection with FIGS. 4, 5, and 6.
FIG. 4 is the case of condition,
DN+WN=(A).sub.HEX +(4).sub.HEX <(10).sub.HEX
Then, reading of the next word data and writing of process result do not
take place.
FIG. 5 is the case of condition,
DN+WN=(E).sub.HEX +(4).sub.HEX >(10).sub.HEX
Then, reading of the next word data and writing of process result take
place.
FIG. 6 is the case of condition,
SN+WN=(D).sub.HEX +(4).sub.HEX >(10).sub.HEX
and
DN+WN=(2).sub.HEX +(4).sub.HEX <(10).sub.HEX
Then, reading of the next SRC word data takes place, but writing of the
process result does not take place.
Attempting to implement the image processing of the present invention using
a conventional processing system involves the following drawbacks.
(1) The conventional microprocessor of word addressing type needs register
rotation and word boundary check by software in implementing bit block
operations, resulting in a complex system control.
(2) Fetching of data from the processing areas X.sub.A and X.sub.B needs
different access timing depending on the current bit position with respect
to the word boundary, resulting in a complex software control.
(3) The amount of data stored in the memory areas M1 and M2 will range as
much as from 100 kilo-bytes to several mega-bytes, and the process shown
in FIG. 3 with the bit width WN being set as large as one byte (8 bits)
will take a total number of steps of the order of 10.sup.6, and therefore
the number of processing steps needs to be reduced drastically.
Furthermore, the conventional microprocessor merely allows bit operations
such as arithmetic shift, logical shift, bit set, bit reset, etc. But as
to other arithmetic and logic operations, etc., it is impossible to carry
out the operations except only in a fixed bit length such as a byte or
word. On this account, in order to achieve "raster operation" on a bit-map
display having a memory in correspondence at each point of on/off control
to the display screen for implementing an image process between separate
rectangular areas of arbitrary size on the screen, the above-mentioned bit
operations do not suffice the purpose, but operations of data with any bit
width at any position in each word becomes necessary. If such operations
are intended to be performed using a microprocessor, input data is shifted
for bit alignment, an operation is conducted on the data, the resultant
data is shifted for alignment with another data to be merged, and after
the merging operation the resultant data is stored in the original memory
location. These sequential operations take too long a time, and fast image
processing cannot be expected.
There is a method of solving this problem, in which there is added to the
system a barrel shifter that is capable of multi-bit shift at the same
operating speed as the single-bit shift, and a merging circuit. However,
despite the capability of bit alignment by the barrel shifter, the
processor is limited to fixed word-length operations and external memory
access usually in 8-bit or 16-bit length, and the restricted hardware
ability for implementing arbitrary bit width operations need to be covered
by complex software processes through the use of simple bit operations. An
example of the processor for implementing the foregoing operations is
Micro Processor, model Am 29116, manufactured by ADVANCED MICRO DEVICES.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a method and apparatus for bit
operation with the intention to simplify and speed up the computation
between data with arbitrary number of bits at arbitrary position in each
data word.
Another object of this invention is to provide a bit processing system
capable of easily accessing an external data memory under word address
control for the internal processing under bit address control.
Still another object of this invention is to provide a bit operation unit
capable of easily executing an arithmetic and logic operation for bits
with any number of bits at any position in each data word.
A further object of this invention is to provide a bit operation processing
system capable of bit and word address control and external memory access
control on a hardware basis so that the overhead software processing is
reduced to enhance the system performance.
In order to achieve the above objectives, this invention has features as
follows.
(1) Internal computations are controlled entirely on the basis of bit
addressing.
(2) A bit address operation unit is provided for bit addressing control in
addition to the word address operation unit for word addressing control.
(3) The bit address operation unit operates to add the current operation
starting bit address to the bit width of bits to be operated.
(4) The bit address and word address operation units have an interface
through the carry signal produced by the bit address operation unit.
(5) The carry signal of the bit address operation unit, when seen from the
internal processing control, is an anticipation signal indicating that the
current starting bit position will reach beyond the word boundary in the
next operation cycle. Accordingly, the carry signal is used to trigger the
external memory access for fetching word data necessary for the bit
operation at the word boundary.
(6) The bit address and word address operation units, share the hardware
components, but have the distinct logical functions relating through the
carry signal.
(7) The bit address operation unit operates cyclically in a word period,
and its output represents the relative bit address counted from each word
boundary.
(8) The carry signal produced at a certain bit position of the bit address
operation unit creates the boundary of words of 2.sup.n bits.
(9) The bit address operation unit performs addition of an operation bit
width for each register independently, allowing bit operations of
arbitrary number of bits.
On the other hand, in order for the bit-map display to achieve operation
between data of rectangular screen areas, i.e., raster operation, it is
necessary to achieve operation between data with any bit width at any
position in the data word. For the computation of data with any bit width
by a fixed bit-width processor, the absent bit positions of input data
need to be filled. In simple arithmetic operations, a fixed bit width
processor can deal with data with reduced number of bits by filling 0's
bits in the lower absent bit positions to obtain a correct result
including the carry bit. In the carry adding operation, lower absent bit
positions must be filled with 1's bits to obtain a correct result. Logical
operations between data are implemented for each corresponding bit
separately, and the number of significant bits is arbitrary for the
processor to obtain a correct result, except for the flags, which values
are correct when absent bit positions are filled with 0's or 1's bits
selectively. Accordingly, in carrying out an arithmetic or logic operation
for data with arbitrary number of bits, input data are placed at high
order bit positions of the processor, with absent bit positions being
filled with 0's bits or 1' s bits depending on the type of operation,
thereby to obtain a completely correct result.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram for explaining the image data processing intended by
the present invention;
FIG. 2 is a diagram for explaining the operation of the modification unit
(MFY) shown in FIG. 1;
FIG. 3 is a flowchart showing the operational procedure of the modification
unit when the image processing of the present invention, as explained with
reference to FIG. 1, is implemented in the conventional system;
FIGS. 4, 5 and 6 are diagrams for explaining the operation shown by the
flowchart of FIG. 3;
FIG. 7 is a block diagram showing the bit data processing system embodying
the present invention;
FIG. 8 is a table for explaining the bit width of computation by the
modification unit;
FIG. 9 is a table for explaining the relation between the carry signal
produced by the bit address operation unit and the access timing;
FIG. 10 is a flowchart showing the image processing operation carried out
by application of this invention;
FIG. 11 is a flowchart showing part of the process of FIG. 10 conducted by
the memory interface unit (MIF);
FIGS. 12, 13 and 14 are diagrams for explaining the operations shown in
FIGS. 10 and 11;
FIG. 15 is a block diagram showing in detail the arrangement of the bit
operation unit shown in FIG. 7;
FIG. 16 is a table showing the output function of the operand data slicing
circuit 3 shown in FIG. 15;
FIG. 17 is a table showing the output function of the operating data
slicing circuit 4 shown in FIG. 15;
FIG. 18 is a table listing the types of operation performed by the
processing unit 5 shown in FIG. 15;
FIG. 19 is a table showing the merged data R2 shown in FIG. 15;
FIG. 20 is a table showing the writing mask data M shown in FIG. 15;
FIG. 21 is a table showing the output function of the operation result
register 7 shown in FIG. 15;
FIG. 22 is an illustration showing the execution of reaster operation on
the bit-map display;
FIG. 23 is a diagram for explaining the operation of the bit processing
system of the case with displaced bit positions; and
FIG. 24 is a block diagram showing the system configuration for
implementing the image processing according to this invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
In FIG. 24 showing the image processing system, the bit operation processor
110 is controlled by CPU 100 of the host computer to perform image
processing such as expansion, reduction, rotation and merging of image
patterns, (1). In implementing the image processing, the bit operation
processor 110 fetches data from the image data memory 120, processes the
data, 2, and stores the resultant data in the image data memory 120 so
that it is displayed on the CRT display unit 130, (3).
This invention is intended to provide means for implementing the
above-mentioned operations (2, 3) of reading and writing the image data
memory 120 for data of any bit width at any positions in the data word.
First, bit position control necessary for bit operation will be described
with reference to FIG. 7 showing an embodiment of the inventive bit
operation processor.
The arrangement of FIG. 7 includes a word address operation unit ADW, a bit
operation unit BOU for accessing data in the aforementioned memory areas
M1 and M2 in the image data memory 120, the bit operation unit BOU
performing the aforementioned three functions (1), (2) and (3) by rotating
the register contents depending on the bit addresses SN and DN of the
processing areas X.sub.A and X.sub.B, a bit register unit ADB, and a bit
address operation unit BR including an operation bit width register WNR
for storing the value of operation bit width WN, a source bit address
register SNR for storing the operation starting bit position SN for the
processing area X.sub.B and a destination bit register DNR for storing the
operation starting bit position DN for the processing area X.sub.A. Signal
line AC is for the carry produced by the bit address operation unit ADB,
signal bus MA is for the word address produced by the word address
operation unit ADW, and signal bus D is for word data, through which buses
image data is transferred with the memory areas M1 and M2. The bit
register unit BR and the bit address operation unit ADB in combination
constitute a bit address control unit BM. The contents of the bit register
unit BR, i.e., WN, SN and DN, are used by the bit operation unit BOU.
The bit operation unit 110 fetches data from separate memory areas M1 and
M2 within the image data memory 120 via the memory interface unit MIF.
There are two cases of reading the memory areas M1 and M2 depending on the
starting bit position na (nb) of a data segment with a bit width WN to be
processed currently in a data word with a bit width of L as follows.
(a) New word data is required for the subsequent operation, in case,
##EQU1##
(b) Current word data suffices for the subsequent operation, in case,
##EQU2##
The above conditions are tested on a hardware basis through the provision
of an L-bit bit address operation unit ADB for adding values na (nb) and
WN, with the decision being made depending on the presence or absence of
the carry signal AC from the operation unit ADB. The carry signal AC
indicates the need of next word data reading, and it is used to trigger
the word address operation unit ADW for addressing the next data word. In
this way, the bit operation unit 110 makes access to the memory areas M1
and M2 only when new word data becomes necessary for processing.
In describing operation unit 110, the operation of the bit address control
unit BM will first be explained.
The bit address control unit BM operates on the bit address operation unit
ADB to add a starting bit address SN (DN) in the register SNR (DNR) to a
operation bit width WN in the register WNR to evaluate the starting bit
address SN (DN) for the next operation, and stores the result in the
register SNR (DNR).
Generally, image processing is conducted between image data in two separate
screen areas, and therefore both corresponding memory areas X.sub.A and
X.sub.B under process have distinct starting bit addresses which need to
be stored separately, DN in DNR and SN in SNR. The operation bit width WN
is constant during the entire process and common to both processing areas
X.sub.A and X.sub.B, and it is stored in the single register WNR.
The bit address operation unit ADB is of four bits as mentioned previously,
providing a result in the range of (0).sub.HEX to (F).sub.HEX.
Accordingly, the output of the bit address operation unit ADB represents
the bit position between contiguous word boundaries. However, the
operation bit width WN used by the bit operation unit BOU requires bit
range including (10).sub.HEX beyond the word boundary in addition to
(1).sub.HEX to (F).sub.HEX. On this account, the bit operation unit BOU is
designed to interpret the operation bit width WN as shown by the table of
FIG. 8. In this way, the bit address control unit BM calculates the
relative bit address within a 16-bit data word.
The word address operation unit ADW operates to increment the word address
in response to a signal from the bit address control unit BM. The
following describes the interface between the ADW and the bit address
operation unit ADB in BM for the word addressing operation. The word
address operation unit ADW is notified by the ADB of the overrun of the
word boundary by use of the carry signal AC produced by the ADB. However,
the value which any of the bit address operation unit ADB and registers
WNR, SNR and DNR, which have a capacity of four bits is (0).sub.HEX to
(F).sub.HEX, therefore, addition of WN and SN (or DN) does not always
produce the carry signal AC to meet the purpose. For example, in case of
WN=(F).sub.HEX, SN=(0).sub.HEX for the 16-bit operation (see FIG. 8), the
following bit address calculation does not create the carry signal AC
despite the case that the bit address will reach beyond the word boundary
in the next operation.
WN+SN=(F).sub.HEX +(0).sub.HEX =(F).sub.HEX
On this account, the address increment operation by the bit address
operation unit ADB must include addition of one so that the carry signal
AC is produced as desired, as follows.
(WN+1)+SN=(F).sub.HEX +(1).sub.HEX +(0).sub.HEX =(10).sub.HEX (4)
As mentioned above, a necessary carry signal AC can be produced by adding
"1", and addition of "1" becomes indispensable.
The aforementioned carry signal AC can be used as a decision signal
indicating as to whether or not the bit position will reach beyond the
current word boundary in the next operation cycle. Accordingly, the carry
signal AC from the bit address operation unit ADB can be used as, (1) an
anticipation signal indicating the need of fetching the next word data,
and (2) a trigger signal to the word address operation unit ADW for
generating the address of word data to be fetched. In other words, the
carry signal AC from the bit address operation unit ADB can be used for
timing the access operation of the memory interface unit MIF to the
processing areas X.sub.A and X.sub.B, as shown in FIG. 9. Due to separate
registers SNR and DNR for storing the starting bit addresses SN and DN,
the above-mentioned functions (1) and (2) of the carry signal AC can
reflect on the processing areas X.sub.A and X.sub.B independently.
FIG. 10 shows in flowchart the operation of the foregoing embodiment of
this invention applied to the image processing system shown in FIG. 1. In
a sequence of operations, a processing step P1 sets the word address
B.sub.0 and bit address nb (SN=nb) of SNR for the operation starting bit
position for the processing area X.sub.B, step P2 sets the word address
A.sub.0 and bit address na (DN=na) of DNR for the operation starting bit
position for the processing area X.sub.A, step P3 is the function of the
bit operation unit BOU, step P4 calculates the next operation starting bit
position SN for the processing area X.sub.B using the bit address
operation unit ADB and word address operation unit ADW, step P5 similarly
calculates the next operation starting bit position DN for the processing
area X.sub.A, step XP1 reads a word data in the processing area X.sub.B,
step XP2 writes the operation result in the processing area X.sub.A, step
XP3 reads a word data in the processing area X.sub.A, step PB1 tests the
completion of process for each of rasters Ro-Rm, and steps XB1 and XB2
test the results of executions in the above steps XP1, XP2 and XP3 in
accordance with the presence or absence of the carry signal AC.
The decision steps XB1 and XB2 will be explained in more detail in the
following.
(1) It is tested as to whether the data segment to be processed next ranges
within the current data word or beyond the word boundary.
(2) At the decision step XB1, if the segment is within the current data
word (case 1 in FIG. 9), the step XP1 is skipped, or if the segment
reaches beyond the word boundary (case 2 in FIG. 9), the step XP1 is
executed to read the next word data from the processing area X.sub.B.
(3) At the decision step XB2, if the segment is within the current word
(case 3 in FIG. 9), the steps XP2 and XP3 are skipped, or if the segment
reaches beyond the word boundary (case 4 in FIG. 9), the step XP3 is
executed to read the next word data from the processing area X.sub.A.
(4) In case 4, the processing step XP2 for writing the processing area
X.sub.A is executed by the following reason. The processing area X.sub.A
is included in the memory area M1 as shown in FIG. 1, and it is also
written the result of processing. When the next starting bit position
calculated basing on the value of DN reaches beyond the word boundary, it
indicates that the operation for one word data has completed.
Namely, the conventional system tests the word boundary condition for
fetching the next word data on a software basis, whereas the inventive
system employs a bit address operation unit ADB for anticipating the need
of memory access, allowing the continuous execution of the internal bit
operational process while dealing with external word data.
Decisions made by the steps XB1 and XB2 are based on the carry signal AC
produced by the bit address operation unit ADB as described above, and the
carry signal AC can readily be distinguished among the four cases shown in
FIG. 9 depending on the use of register DNR or SNR. Accordingly, by
implementing the decision process for the four cases as shown in FIG. 11
in the memory interface unit MIF, a processing step group X1 including the
steps XB1 and XP1, and a processing step group X2 including the steps XB2,
XP2 and XP3, shown in FIG. 10, can be eliminated. In FIG. 11, steps P1-P5
and PB1 are identical to those shown in FIG. 10.
The foregoing operations of four cases are shown in FIGS. 12, 13 and 14, in
which initial values are set as: the operation starting bit address
SN=(5).sub.HEX and word address Bo for the processing area X.sub.B ; the
operation starting bit address DN-(A).sub.HEX and word address Ao for the
processing area X.sub.A ; the operation bit width WN=(3).sub.HEX. FIG. 12
is for cases 1 and 3, FIG. 13 is for case 4, and FIG. 14 is for case 2 in
FIG. 9.
Next, an embodiment of this invention with the intention of fast data
processing between rectangular areas on the bit-map display, i.e., raster
operation, will be described in connection with FIGS. 15 through 23.
In FIG. 15 showing in detail the bit operation unit BOU in the bit
operation processor of FIG. 7, the arrangement includes an operand data
register 1, an operating data register 2, an operand data slicing circuit
3, an operating data slicing circuit 4, a processing unit 5, a data
merging circuit 6, an operation result register 7, a source bit address
register SNR, a destination bit address register DNR, an operation bit
width register WNR, a merging address register 11, an operation control
register 12, and an operation command decoder 13. In this specification,
term "operating data" is used to mean one member of an arithmetic/logic
operation, such as X in Z=X+Y, while term "operand data" to mean another
member of the operation, such as Y in Z=X+Y. The block diagram further
indicates operand data I1, operating data I2, sliced operand data I3,
sliced operating data I4, operand data slicing address IS1, operating data
slicing address IS2, slicing bit width W, operation result R1, merging
address D, writing mask data M, merged data R2, stored result data R3,
operation command code FC, and operation decode data F. Fetching of data
from the image data memory 120 to the registers 1 and 2, and storing of
data from the register 7 in the memory are conducted by making access to
the image data memory 120 through the memory interface unit MIF as shown
in FIG. 7.
For the simplicity of the following description on the operation of the
above arrangement, the processing unit 5 is assumed to have 4 bits in
relation to operand data I1, operating data I2, mask data M and merged
data R2 each having 8 bits, twice the operation bit width, sliced operand
data I3, sliced operating data I4 and computation result R1 each having 4
bits, identical to the operation bit width, and operand data slicing
address IS1, operating data slicing address IS2, slicing bit width W and
merging address D each having 2 bits, derived from the 2-bit processing
unit 5.
FIG. 16 is the output function table for the operand data slicing circuit
3. In the table, IS1.sub.0 and IS1.sub.1 are the high-order bit and
low-order bit of the operand data slicing address IS1, W.sub.0 and W.sub.1
are the high-order bit and low-order bit of the slicing bit width W,
I3.sub.0 -I3.sub.3 l are 4-bit sliced operand data (I3.sub.0 being highest
bit, I3.sub.3 lowest), I1.sub.0 -I1.sub.7 are 8-bit operand data (I1.sub.0
being highest bit, I1.sub.7 lowest), and F is the operation decode data.
The operand data slicing circuit 3 produces `F` at I3.sub.1 -I3.sub.3 when
W equals to 0 (W.sub.0 =0, W.sub.1 =0), produces `F` at I3.sub.2 and
I3.sub.3 when W equals to 1 (W.sub.0 =0, W.sub.1 =1), produces `F` at
I3.sub.3 when W equals to 2 (W.sub.0 =1, W.sub.1 =0), and produces an
effective data at I3.sub.0 -I3.sub.3 when W equals to 3 (W.sub.0 =1,
W.sub.1 =1).
Namely, the slicing bit width W is actually added by one (W+1), so that the
circuit performs slicing of data ranging from 1 bit to 4 bits. The operand
slicing address IS1 specifies the highest order bit I1 through W+1th bit
of operand data I1 when IS1 equals to 0 (IS1.sub.0 =0, IS1.sub.1 =0),
specifies the second bit I1 through W+1th bit of operand data I1 when it
is equal to 1 (IS1.sub.0 =0, IS1.sub.1 =1), specifies the third bit
I1.sub.2 and fourth bit I1.sub.3 when IS1 equals to 2, and specifies the
fourth bit I1.sub.3 for slicing when IS1 equals to 3.
FIG. 17 is the output function table for the operating data slicing circuit
4, which operates identically to the operand data slicing circuit 3 with
its input and output signals IS1, I1 and I3 being replaced with IS2, I2
and I4.
FIG. 18 a table of operation command codes FC, operation decode data F and
types of operations. In the table, symbol A represents an operand data, B
represents an operating data, "+" signifies logical sum, ".multidot."
signifies logical product, "-" signifies negation, ".sym." signifies
exclusive logical sum, "plus" signifies arithmetic addition, "minus"
signifies arithmetic subtraction, "carry" represents the value of carry
flag, and "borrow" represents the value of borrow flag.
FIGS. 19 and 20 are the output function tables for the merging circuit 6,
showing merged data R2 and writing mask data M, respectively. Each signal
is suffixed to indicate bit positions in the same way as for the signals
in FIGS. 16 and 17. The merged data R2 is not dependent on the slicing bit
width W, but is a function of the merging address D and operation result
R1. With D being equal to 0, the merged data R2 is given at bit positions
R2.sub.0 -R2.sub.3 a 4-bit operation result R1.sub.0 -R1.sub.3 ; at D=1,
R2.sub.1 -R2.sub.4 are given the operation result; at D=2, R2.sub.2
-R2.sub.5 are given the operation result; and at D=3, R2.sub.3 -R2.sub.6
are given the operation result. The remaining bit positions of the merged
data R2 are filled with "0".
Writing mask data M is a function of merging address D and slicing bit
width W, as shown in the table of FIG. 20. With the slicing bit width W
being 0, writing mask data M has "1" at one bit position and "0" at
remaining bit positions. With W=1, data M has "1" at two contiguous bit
positions and "0" at remaining bit positions. With W=2, data M has "1" at
three consecutive bit positions, and with W=3, data M has "1" at four
consecutive bit positions and "0" at remaining bit positions. Bit
positions of writing mask data having "1" are determined from the merging
address D, i.e., with D=0, W+1 bits from M.sub.0 becomes "1"; with D=1,
W+1 bits from M.sub.1 becomes "1"; with D=2, W+ 1 bits from M.sub.2 become
"1"; and with D=3, W+1 bits from M.sub.3 become "1", with remaining bit
positions becoming "0".
FIG. 21 shows the output function table for the operation result register
7. The 8-bit register 7 provides outputs as a function of merged data R2
and writing mask data M. With bit i of writing mask data M being "0",
i.e., Mi=0, bit i of stored data R3, i.e., R3.sub.i, is unchanged, while
with Mi being "1", the R3.sub.i is overwritten by bit i of merged data R2,
i.e., R2i, where i takes an arbitrary value ranging 0 through 7.
FIG. 22 illustrates the execution of raster operation on the bit-map
display, in which a pair of image data in rectangular areas SA and SB are
processed to obtain the result in a rectangular area DST. The bit-map
display has a memory which is arranged in the 8-bit or 16-bit word length
for reading and writing as in the usual memory. The rectangular data areas
SA, SB and DST correspond to bit blocks of memory regardless of word
boundaries. Slicing of a bit block within a word or beyond a word is
treated by the bit operation processor which operates as shown in FIG. 23.
In this embodiment of the bit operation processor, the operation will be
described with the following assumption of settings. The operand data Il
has a starting bit position of IS1=1, operating data I2 has IS2=3, and
operation bit width W is 2 bits. The operand data I1 has value `100` on
bits 1-3, and operating data I2 has value `001` on bits 3-5.
The operand data slicing circuit 3 responds to the values IS1=1 and W=2 to
slice three bits (`100`) bit position to form sliced operand data I3. In
the same way, the operating data slicing circuit 4 produces sliced
operating data I4. The processing unit 5 performs operation between the
sliced data I3 and I4, and provides the result R1. In the example of FIG.
23, the processing unit 5 is instructed to execute logical summation for
the given data. The merging circuit 6 responds to the values of W and D to
merge the high-order 3 bits (`101`) of the operation result R1 into 3 bits
of the stored data R3 starting at bit 3. By the above operations, operand
data I1 and operating data I2 are sliced and, after operation between the
data, the result is merged into the stored data R3.
Although logical summation has been explained in the above embodiment,
other logical operations such as negation (NOT) and logical multiplication
(AND) can obviously be executed. For arithmetic operations, when the bit
width of operating data is smaller than the operation bit width (4 bits)
of the processing unit 5 as in the case of FIG. 23, lower bit(s) are
filled with "0". Arithmetic operations between zeros results in zero
without the occurrence of the carry or borrow and does not affect the
operation result of high-order bits, and therefore arithmetic operations
with less number of bits can be executed. For addition of carry, the
operation decode data F becomes 1, and the occurrence of carry is
propagated up to the effective bit position, at which the carry bit is
added.
Although in the above embodiment the operation decode data F is used only
for the sliced operand data IS3, other operation decode data may be used
for the sliced operating data IS4 to carry out the execution identically.
As described above, the present invention is effective in controlling the
bit position of data for bit operation, as follows.
(1) By addition of a bit address operation unit ADB to the conventional
word address operation unit ADW, control of operation between data with
different starting bit positions SN and DN in each word data can be
simplified.
(2) By using the carry signal AC of the bit address operation unit ADB for
incrementing the word address operation unit ADB and by providing
registers SNR and DNR separately, the word data memory areas X.sub.A and
X.sub.B can readily be accessed independently of the internal bit
processing.
(3) By implementing bit address and word address control and memory access
control on a hardware basis, the process can be simplified down to 1/3 or
less in terms of processing steps as compared with the conventional system
(see FIGS. 3 and 11), whereby speed-up of process is accomplished.
(4) Since execution of operational processes for any number of bits at any
bit position in word data can be made, speed-up of bit operation is
accomplished.
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