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United States Patent | 5,156,993 |
Su | October 20, 1992 |
A process for producing a random access memory cell having an improved capacitor structure that thereby permits greater integration. The capacitor is a merged combination of a stacked trench and a stacked capacitor which has at least two plates separated by a dielectric layer. The plates are formed of polysilicon and extend partially over the gate region, over the source region, over the sidewalls and bottom of a trench, and partially over the field oxide.
Inventors: | Su; Wen-Doe (Yun Lin, TW) |
Assignee: | Industrial Technology Research Institute (Chutung, TW) |
Appl. No.: | 568945 |
Filed: | August 17, 1990 |
Current U.S. Class: | 438/244; 257/E21.008; 257/E21.651; 257/E27.094 |
Intern'l Class: | H01L 021/70 |
Field of Search: | 437/38,47,48,52,60,191,193,195,203,228,233,235,919 357/23.6 148/DIG. 50 156/643 |
4894696 | Jan., 1990 | Takeda et al. | 357/23. |
4921816 | May., 1990 | Ino | 357/23. |
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0307257 | Dec., 1989 | JP. | |
138207 | Oct., 1984 | GB. |