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United States Patent | 5,107,459 |
Chu ,   et al. | April 21, 1992 |
A stacked bit-line architecture utilizing high density cross-point memory arrays forms a DRAM semiconductor memory device. The true and complementary bit-line pairs connected to the respective memory cell arrays are formed in two metal layers, one above the other. A bit-line interconnector region is provided that uses a third interconnection layer together with the first and second layers to transpose the vertical stacking of each pair and to transpose the planar alignment of adjacent bit-line pairs. The DRAM memory cell array has a high density cross-point memory cell architecture that behaves electrically as a folded bit-line array.
Inventors: | Chu; Christopher M. (Irvine, CA); Dhong; Sang H. (Mahopac, NY); Hwang; Wei (Armonk, NY); Lu; Nicky C-C. (Yorktown Heights, NY) |
Assignee: | International Business Machines Corporation (Armonk, NY) |
Appl. No.: | 513315 |
Filed: | April 20, 1990 |
Current U.S. Class: | 365/63; 257/302; 257/E27.096; 365/72; 365/149 |
Intern'l Class: | G11C 005/06; G11C 011/24 |
Field of Search: | 365/51,63,149,72 |
4156938 | May., 1979 | Proebsting et al. | 365/63. |
4402063 | Aug., 1983 | Wittwer | 365/154. |
4476547 | Oct., 1984 | Miyasaka | 365/205. |
4570241 | Feb., 1986 | Arzubi | 365/205. |
4710789 | Dec., 1987 | Furutani et al. | 365/51. |
4816884 | Mar., 1989 | Hwang et al. | 357/23. |
4922453 | May., 1990 | Hidaka | 365/63. |
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