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United States Patent |
5,107,149
|
Platt
,   et al.
|
April 21, 1992
|
Linear, continuous-time, two quadrant multiplier
Abstract
A linear voltage-to-current converter (LVCC) circuit includes two
transistors, one P-channel and one N-channel. The input voltage is applied
to the gates of both transistors. The drains of the two transistors are
connected. The source of the p-type transistor is connected to a first
voltage rail, and the source of the N-channel is connected to a second
voltage rail of lower voltage. The output is the difference between the
current through the P-channel transistor and the N-channel transistor. A
linear current-to-voltage converter (LCVC) circuit is similar to the LVCC
circuit, except that the gates of the transistors are tied to the drains
of the transistors. The input current is supplied to the drains, and the
output voltage is the voltage of the drains.
Inventors:
|
Platt; John C. (Mountain View, CA);
Wall; Michael F. (Sunnyvale, CA);
Gribble; Glenn E. (San Jose, CA);
Mead; Carver A. (Pasadena, CA)
|
Assignee:
|
Synaptics, Inc. (San Jose, CA)
|
Appl. No.:
|
746960 |
Filed:
|
August 19, 1991 |
Current U.S. Class: |
327/357; 327/355 |
Intern'l Class: |
H03F 003/45 |
Field of Search: |
328/160
307/529,490,571,584,585,582,500,501,498
|
References Cited
U.S. Patent Documents
3714462 | Jan., 1973 | Blackman | 328/160.
|
4071777 | Jan., 1978 | Herrmann | 328/160.
|
4556804 | Dec., 1985 | DeWitt | 307/584.
|
4978873 | Dec., 1990 | Shoemaker | 328/160.
|
5049758 | Sep., 1991 | Mead et al. | 307/311.
|
5059320 | Oct., 1991 | Anderson et al. | 330/307.
|
Other References
Evert Seevinck, "A Versatile CMOS Linear Transconductor/Square-Law Function
circuit", Jun. 1987, pp. 365-377.
|
Primary Examiner: Miller; Stanley D.
Assistant Examiner: Tran; Sinh N.
Attorney, Agent or Firm: D'Alessandro; Kenneth
Parent Case Text
RELATED APPLICATIONS
This application is a division of co-pending application, Ser. No.
07,629,470, filed Dec. 18, 1990.
Claims
What is claimed is:
1. A linear, two-quadrant multiplier circuit, including:
a first input node,
an output node,
a current load connected to said output node,
a first voltage rail connected to a source of a first electrical potential,
a second voltage rail connected to a source of a second electrical
potential more negative than said first electrical potential,
a first P-channel MOS transistor, having its gate connected to a second
input node, and its drain connected to said output node,
a second P-channel MOS transistor, having its gate connected to said second
input node, and its source connected to said output node,
a third P-channel MOS transistor, having its gate connected to said input
node, its drain connected to the source of said first P-channel MOS
transistor, and its source connected to said first voltage rail,
an N-channel MOS transistor, having its gate connected to said input node,
its drain connected to the drain of said second P-channel MOS transistor,
and its source connected to said second voltage rail,
the sizes of said third P-channel MOS transistor and said N-channel MOS
transistor being chosen such that the quadratic dependance of the current
through said third P-channel MOS transistor balances the quadratic
dependance of the current through said N-channel MOS transistor and both
said third P channel MOS transistor and said N-channel MOS transistor
being operated above threshold and in saturation.
2. A linear, continuous-time, two-quadrant multiplier circuit, including:
a first input node for a first input voltage,
a second input node for a second input voltage,
a floating node,
an output node,
a current load connected to said output node,
a first voltage rail connected to a source of a first electrical potential,
a MOS transistor of a first conductivity type, having its gate connected to
said floating node, its drain connected to said output node, and its
source connected to said first voltage rail,
a MOS transistor of a second conductivity type, having its gate connected
to said floating node, its drain connected to said output node, and its
source and substrate connected to said second input node,
a first capacitor connected between said first input node and said floating
node,
a second capacitor connected between said second input node and said
floating node,
the sizes of said MOS transistors being chosen such that the quadratic
dependance of the current through said MOS transistor of said first
conductivity type balances the quadratic dependance of the current through
said MOS transistor of said second conductivity type and both said MOS
transistors being operated above threshold and in saturation.
3. A linear, continuous-time, two-quadrant multiplier circuit, including:
a first input node for a first input voltage,
a second input node for a second input voltage,
a floating node,
an output node,
a current load connected to said output node,
a first voltage rail connected to a source of a first electrical potential,
a MOS transistor of a first conductivity type, having its gate connected to
said floating node, its drain connected to said output node, and its
source connected to said first voltage rail,
a MOS transistor of a second conductivity type, having its gate connected
to said floating node, its drain connected to said output node, and its
source and substrate connected to said second input node,
a first capacitor connected between said first input node and said floating
node,
a second capacitor connected between said second input node and said
floating node,
the sizes of said MOS transistors being chosen such that the quadratic
dependance of the current through said MOS transistor of said first
conductivity type balances the quadratic dependance of the current through
said MOS transistor of said second conductivity type and both said MOS
transistors being operated above threshold and in saturation,
means for injecting electrons onto said floating node, and
means for removing electrons from said floating node.
Description
BACKGROUND OF THE INVENTION
1. Field Of The Invention
The present invention relates to electronic circuits and to circuits which
may be integrated on a single piece of material to form an integrated
circuit. More specifically, the present invention relates to circuits for
performing linear conversion between voltages and currents.
2. The Prior Art
There are known circuits in the prior art which use CMOS transistors to
convert voltage to current in a linear fashion. Much work has been done
using CMOS transistors in their ohmic region. For example, the paper Y.
Tsivadis, M. Banu, J. Khoury, "Continuous Time MOSFET-C Filters in VSLSI,
IEEE Trans. on Circuits and Systems", Vol. CAS-33, pp. 125-140 (1986)
describes use of multiple transistors to cancel the nonlinearity of
transistors while they are ohmic. The circuits described draw current from
the input node. Also, because transistors are used in their ohmic regime,
the input voltage range of the circuits is limited. The circuits described
therein can also be used as linear continuous time multipliers.
There has also been work using CMOS transistors in saturation for the
conversion of voltage to current. The work describes use of a special
process to generate depletion mode devices. This work is discussed in the
paper P. A. Shoemaker, I. Lagnado, R Shimabukuro, "Artificial Neural
Network Implementations with Floating Gate MOS Devices", from the
proceedings "Hardware Implementations of Neural Nets and Synapses",
NSF/ONR Workshop, P. Mueller, ed. The same research group published
further work on adaptation of the circuits: R. L. Simabukuro, R.E. Reedy,
G.E. Garcia, "Dual Polarity Nonvolatile MOS Analog Memory (MAM) Cell for
Neural-Type Circuitry". Electronics Letters, Vol. 24, No. 19, pp.
1231-1232, Sep. 15, 1988.
No work is known to the inventors involving the use of saturated MOS
transistors in linear voltage/current conversion circuits which do not
draw input current and which can be fabricated using a conventional CMOS
process.
BRIEF DESCRIPTION OF THE INVENTION
A first aspect of the present invention includes circuits which linearly
convert a voltage to a current and circuits which linearly convert a
current to a voltage.
The linear voltage-to-current converter (LVCC) circuit includes two
transistors, one P-channel and one N-channel. The input voltage is applied
to the gates of both transistors. The drains of the two transistors are
connected. The source of the p-type transistor is connected to a first
voltage rail, and the source of the N-channel is connected to a second
voltage rail of lower voltage. The output is the difference between the
current through the P-channel transistor and the N-channel transistor. The
linear current-to-voltage converter (LCVC) circuit is similar to the LVCC
circuit, except that the gates of the transistors are tied to the drains
of the transistors. The input current is supplied to the drains, and the
output voltage is the voltage of the drains.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1a and 1b are schematic diagrams of linear voltage to current
converter circuits according to a presently preferred embodiment of the
invention.
FIG. 2 is a graph showing a family of exemplary transfer curves for the
LVCC circuit of FIG. 1a.
FIG. 3 is a schematic diagram of a two-quadrant linear multiplier according
to a presently preferred embodiment of the invention.
FIG. 4 is a schematic diagram of a continuous time two-quadrant linear
multiplier according to a presently preferred embodiment of the invention.
FIG. 5 is a graph showing the transfer function for the circuit of FIG. 4,
illustrating the output current as a function of the input voltage V.sub.x
for various values of the input voltage V.sub.y.
FIGS. 6a and 6b are schematic diagrams of linear current-to-voltage
converter (LCVC) circuits according to a presently preferred embodiment of
the present invention.
FIG. 7 is a graph showing the transfer function of the LCVC circuit of FIG.
6a.
FIG. 8a is a block diagram of a current negator (CN) circuit according to
the present invention showing it to be a combination of an LCVC circuit
driving a LVCC circuit.
FIG. 8b is a schematic diagram of a CN circuit according to one presently
preferred embodiment of the present invention.
FIG. 8c is a block diagram of a CN circuit according to the present
invention, showing it to be the equivalent of two current mirrors sharing
input and output nodes.
FIG. 8d is a schematic diagram of a CN circuit according to a presently
preferred embodiment of the present invention comprising a pair of Wilson
current mirrors.
FIG. 8e is a schematic diagram of a CN circuit according to a presently
preferred embodiment of the present invention comprising a pair of cascode
current mirrors.
FIG. 8f is a schematic diagram of a CN circuit according to a presently
preferred embodiment of the present invention comprising a pair of
multiple stage Wilson current mirrors.
FIG. 8g is a schematic diagram of a CN circuit according to a presently
preferred embodiment of the present invention comprising a pair of
multiple stage cascode current mirrors.
FIG. 9 is a graph showing the transfer function of the CN circuit of FIG.
8b.
FIG. 10a is a block diagram illustrating the use of multiple output stages
with the CN circuits disclosed herein.
FIG. 10b is a schematic diagram of an example of a multiple output CN
circuit according to the present invention.
FIG. 11a is a block diagram of a voltage negator circuit according to the
present invention.
FIG. 11b is a schematic diagram of a voltage negator circuit according to
the present invention.
FIG. 12 is a graph showing the transfer function for the voltage negator
circuit of FIG 11b.
FIG. 13 is a block diagram of an inverting linear voltage-to-current
converter (ILVCC) circuit according to the present invention by combining
a LVCC circuit as an input to drive a CN circuit as an output.
FIG. 14 is a block diagram of a delay line according to a presently
preferred embodiment of the invention including a chain of voltage negator
circuits, like that of FIG. 11, connected in series, with capacitance on
the output of each voltage negator.
FIG. 15 is a block diagram of a linear neuron according to another aspect
of the present invention, fabricated from a plurality of LCTM circuits and
one LCVC circuit.
FIG. 16 is a schematic/block diagram of a sense amplifier circuit according
to the present invention.
DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT
The circuits disclosed within the scope of the present invention are
readily integrable utilizing state of the art integrated circuit
fabrication techniques. Such techniques are well within the general level
of skill in the art of integrated circuit design and will not be included
herein in order to avoid unnecessarily complicating the disclosure.
As an introductory matter, understanding the definitions of some terms used
throughout the specification and claims will facilitate an understanding
of the present invention. If the threshold voltage of a P-channel
transistor is expressed as V.sub.Tp and the threshold voltage of an
N-channel transistor is expressed as V.sub.Tn, a P-channel transistor will
be operating above threshold when its gate voltage is more negative than
.vertline.V.sub.Tp .vertline. with respect to its source, and an N-channel
transistor will be operating above threshold when its gate voltage is more
positive than .vertline.V.sub.Tn .vertline. with respect to its source.
Saturation, as that term is used herein, is defined for a P-channel
transistor as the condition when its gate voltage is no more than
.vertline.V.sub.Tp .vertline. more negative than its drain voltage. For an
N-channel transistor, saturation is defined as the condition where its
gate voltage is no more than .vertline.V.sub.Tn .vertline. more positive
than its drain voltage. For transistors operating in their subthreshold
regions, saturation occurs when the transistor's drain voltage is a few
kt/q units above its source voltage, independent of gate voltage, as
explained in the book Analog VLSI and Neural Systems, Carver A. Mead, p.
37, Addison Wesley Pu. Co. 1989.
According to a presently preferred embodiment of the invention as shown in
FIG. 1aa linear voltage-to-current converter (LVCC) circuit 10 includes
two MOS transistors, one P-channel transistor 12 and one N-channel
transistor 14. An input voltage V.sub.in is applied from an input voltage
node 16 to the gates of both transistors 12 and 14, which are connected
together. The drains of transistors 12 and 14 are connected together to
form an output node 18. The source of the P-channel transistor 12 is
connected to a voltage rail 20 having a first voltage potential V.sub.H,
and the source of the N-channel transistor 14 is connected to a voltage
rail 22 having a second voltage potential V.sub.L, more negative than
V.sub.H. Output node 18 is connected to a current load 24.
For the purposes of the present invention, a current load is an element or
circuit configuration which utilizes the output current while maintaining
the output voltage within a restricted range, such that both P-channel
transistor 12 and N-channel transistor 14 are kept in saturation. Such an
element includes, but is not limited to, a low value resistor or a
conventional current-sense amplifier.
At first glance, the circuit of FIG. 1a appears to be a common inverter
circuit. However, when the transistors 12 and 14 are sized and the circuit
is operated according to the principles disclosed herein, those of
ordinary skill in the art will appreciate that a novel circuit having
novel properties is disclosed.
The current output I.sub.out of LVCC circuit 10 at output node 18 is the
difference between the current through P-channel transistor 12 and the
current through N-channel transistor 14. As the input voltage increases
and N-channel transistor 14 remains in saturation, the current through
N-channel transistor 14 increases quadratically above threshold. As the
input voltage increases, and P-channel transistor 12 remains in
saturation, the current through P-channel transistor 12 decreases
quadratically above threshold.
According to the principles of the present invention, the magnitudes of the
voltages V.sub.H and V.sub.L at the sources of both MOS transistors 12 and
14 are chosen so that the quadratic behavior of MOS transistors 12 and 14
overlap. By choosing the ratio of the sizes of the transistors according
to the principles of the present invention, the quadratic dependance of
the current through P-channel transistor 12 balances the quadratic
dependance of the current through N-channel transistor 14. The output
current I.sub.out at output node 18 then becomes linearly dependent on the
input voltage V.sub.in at node 16
The output current can be approximated mathematically. When both
transistors are in saturation and above threshold according to the present
invention, the output current, I.sub.out, is:
##EQU1##
where V.sub.in is the input voltage at node 16, V.sub.H is the voltage of
the higher voltage rail 20, V.sub.L is the voltage of the lower voltage
rail 22, V.sub.Tp is the threshold voltage of P-channel transistor 12,
V.sub.Tn is the threshold voltage of N-channel transistor 14, .mu..sub.p
is the mobility of P-channel transistor 12, .mu..sub.n is the mobility of
N-channel transistor 14, w.sub.p is the width of P-channel transistor 12,
w.sub.n is the width of N-channel transistor 14, Is is the length of
P-channel transistor 12, l.sub.n is the length of N-channel transistor 14,
and k is a constant of proportionality.
The sizing of the transistors 12 and 14 affects the performance of the
circuit. According to a presently preferred embodiment of the invention,
the widths and the lengths of MOS transistors 12 and 14 are chosen such
that:
##EQU2##
When MOS transistors 12 and 14 are so sized, then the quadratic dependance
of the output current on the input voltage is canceled, leaving only a
linear dependence:
I.sub.out -kR[(V.sub.H +V.sub.T.sub.p).sup.2 -(V.sub.L
+V.sub.T.sub.n).sup.2 +(V.sub.L -V.sub.H +V.sub.T.sub.n
-V.sub.T.sub.p)V.sub.in ] (3)
This equation reduces to:
##EQU3##
The linear dependance of the output current I.sub.out on the input voltage
V.sub.in can be controlled by changing the difference between the higher
voltage source and the lower voltage source. As the difference increases,
the slope of the current-voltage transfer curve increases linearly. This
is illustrated by the family of exemplary transfer curves for the LVCC
circuit shown in FIG. 2.
According to the presently preferred embodiment of the invention, the
circuit of FIG. 1a is operated such that both MOS transistors 12 and 14
are operating in regions above threshold and in saturation. Both MOS
transistors 12 and 14 are operating above threshold when:
V.sub.in -V.sub.T.sub.p <V.sub.H (5)
V.sub.in -V.sub.T.sub.n >V.sub.L (6)
In addition, both MOS transistors 12 and 14 are in saturation when:
V.sub.in -V.sub.Tp >V.sub.out (7)
V.sub.in -V.sub.T.sub.n <V.sub.out (8)
where V.sub.out is the output voltage at output node 18.
The circuit of FIG. 1a operates according to the present invention as an
LVCC circuit when:
V.sub.L <V.sub.in -V.sub.T.sub.n <V.sub.out <V.sub.in -V.sub.T.sub.p
<V.sub.H (9)
With a suitable choice of voltages V.sub.H and V.sub.L for the voltage
rails 20 and 22, the input voltage range over which the transfer function
of the circuit of FIG. is linear can be increased. If the N-channel
transistor 14 falls out of saturation when the P-channel transistor 12
falls below threshold, and the P-channel transistor 12 falls out of
saturation when the N-channel transistor 14 falls below threshold, then
the output current I.sub.out is a linear function of the input voltage
V.sub.in, while the input voltage is between the voltage rails. The
condition for wide-range linearity is:
V.sub.H +V.sub.T.sub.p -V.sub.T.sub.n -V.sub.out -V.sub.L +V.sub.T.sub.n
-V.sub.T.sub.p (10)
The transfer function for wide range linearity is also shown in FIG. 2. The
different curves of FIG. 2 represent the transfer function for different
values of V.sub.L.
In common electronics practice, resistors can be used as linear voltage to
current conversion elements, but are often inappropriate for that use in a
monolithic integrated circuit using MOS technology. The LVCC circuits of
the present invention are superior for use in monolithic CMOS integrated
circuits because their transconductance can be controlled and they draw no
current from their input node.
Referring now to FIG. 1b, another embodiment of a LVCC circuit according to
the present invention is shown. The circuit is identical to the LVCC
circuit of FIG. 1 with the addition of diode connected P-channel MOS
transistor 13 between the source of P-channel transistor 12 and its
voltage rail 20 and diode connected N-channel MOS transistor 15 between
the source of N-channel transistor 14 and its voltage rail 22. The circuit
of FIG. 1b has some advantages over the circuit of FIG. 1a in that it
shows linear behavior over a wider range of input voltage range for a
given current through the transistors. If sufficient power supply voltage
is available, those of ordinary skill in the art will readily see that
additional diode connected transistors may be added to achieve an even
wider voltage range over which linear behavior will be exhibited.
The LVCC circuit of FIG. 1a can be modified to yield a two-quadrant linear
multiplier as shown with reference to FIG. 3. Referring to FIG. 3,
two-quadrant linear multiplier circuit 30 includes P-channel transistor
12, and N-channel transistor 14 of the LVCC circuit of FIG. 1a, having
their sources connected to voltage rails 20 and 22 and their gates
connected together to input node 16. The circuit also includes P-channel
switching transistors 32 and 34 connected in series between the drains of
transistors 12 and 14. The gates of transistors 32 and 34 are connected
together to a switched input 36. Like the LVCC circuit 10 of FIG. 1a, the
output node 18 of the circuit of FIG. 3 is connected to a current load 24.
The two-quadrant linear multiplier circuit 30 is operated within the same
limits disclosed with respect to the LVCC circuit of FI. 1a. When it is
operated within these limits, the output current I.sub.out can be turned
on for a selected amount of time using the switched input 36. The amount
of charge transferred to the output node 18 by the multiplier circuit is
time that the switched input 36 is activated by placing it at a low
voltage such as V.sub.L. Those of ordinary skill in the art will recognize
that switched input 36 may be made high active by using N-channel
transistors in place of P-channel transistors 32 and 34.
Referring now to FIG. 4, a linear, continuous-time, two-quadrant multiplier
(LCTM) circuit 40 according to the present invention is shown. According
to a presently preferred embodiment, LCTM circuit 40 includes a LVCC
circuit of FIG. 1a, having P-channel and N-channel transistors 12 and 14.
The source of P-channel transistor 12 is connected to a voltage rail 20
having a voltage of V.sub.H on it. The gates of P-channel transistor 12
and N-channel transistor 14 are connected together to a floating input
node 42. The drains of P-channel transistor 12 and N-channel transistor 14
are connected together to an output node 18. Floating node 42 is coupled
to a first input node 44 by a first capacitor 46. The source of N-channel
transistor 14 is connected to a second input node 48, which is coupled to
floating node 42 by a second capacitor 50. In a p-well CMOS process, the
source of N-channel transistor 14 is connected to its substrate, which is
the isolated well in which the transistor is fabricated. For an n-well
process, the conductivity types of the P-channel and N-channel transistors
12 and 14 are reversed. A first input voltage V.sub.x is presented at
first input node 44 and a second input voltage V.sub.y is presented at
second input node 48. The voltage V.sub.z on floating node 42 is
determined by the first and second input voltages V.sub.x and V.sub.y on
nodes 44 and 48.
The capacitors 46 and 50 serve as a voltage divider for the voltage V.sub.z
on floating node 42 such that:
##EQU4##
where V.sub.z is the voltage on floating node 42, V.sub.x is the input
voltage on the first input node 44, V.sub.y is the input voltage on the
second input node 48, V.sub.zo is the voltage on floating node 42 when
V.sub.x =V.sub.y =O, C.sub.x is the capacitance of capacitor 46, C.sub.y
is the capacitance of capacitor 50, C.sub.o is the parasitic capacitance
of the floating node 42.
If .alpha. is defined as:
##EQU5##
and .beta. is defined as:
##EQU6##
the current output i.sub.out of the LCTM may be expressed as:
##EQU7##
when transistors 12 and 14 are above threshold and in saturation.
The capacitors 46 and 50 are selected so that .beta.=1/2 or C.sub.y
=C.sub.x +C.sub.o, and the output current I.sub.out is a linear function
of V.sub.y. When the capacitances are properly rationed, the output of the
LCTM circuit may be expressed as:
I.sub.out -2.alpha.kR(V.sub.y -V.sub.y.sub.o)(V.sub.x -V.sub.x.sub.o)(15)
where V.sub.xo =(V.sub.zo +0.5(V.sub.H +V.sub.Tn +V.sub.Tp))/.alpha.and
V.sub.yo =V.sub.H +V.sub.Tp -V.sub.Tn.
The value V.sub.xo can be set by using a number of different analog storage
methods to initialize the floating node. According o a first method, a
transistor 54 may be connected between the floating node 42 and the output
node 18 of the multiplier. The second method consists of connecting a UV
coupler 56 between the floating node 42 and the output node 18 of the
multiplier as disclosed in U.S. Pat. No. 4,935,702 to Mead et al., issued
June 19, 1990. The third method consists of connecting an
injector/tunneling device 58 to the floating node 42, which may be
controlled by the output node 18 of the multiplier circuit 40 (shown by
the dashed connection line) or by other mechanisms, such as are disclosed
in U.S. Patent No. 4,953,928 to Anderson et al., issued Sep. 4, 1990,
which is expressly incorporated herein by reference. In all of these
methods of controlling floating node 42, the fist input node 44 of the
multiplier circuit 40 should be set to the voltage V.sub.xo, the second
input node 48 should be at a voltage somewhere within he normal operating
range of the circuit, and the output node 18 should be isolated form any
other circuit element.
The transfer function for the LCTM circuit 40 of FIG. 4 is shown in FIG. 5.
The output current I.sub.out is shown in FIG. 5 as a function o the input
voltage V.sub.x for various values of the input voltage V.sub.y.
Another aspect of the present invention is a circuit useful as a linear
current-to-voltage converter (LCVC). An LCVC circuit according to a
presently preferred embodiment of the invention is disclosed with
reference to FIG. 6a. An LCVC circuit 60 includes two MOS transistors, one
P-channel transistor 12 and one N-channel transistor 14. An input current
I.sub.in is applied from an input node 16 to the gates of both transistors
12 and 14, which are connected together. The drains of transistors 12 and
14 are connected together to form an output node 18. The output node 18 is
connected to the input node 16. The source of the P-channel transistor 12
is connected to a voltage rail 20 having a first voltage potential
V.sub.H, and the source of the N-channel transistor 14 is connected to a
voltage rail 22 having a second lower voltage potential V.sub.L.
The circuit of FIG. 6a is an example of a current load depicted in FIGS.
1a, 1b, 3 and 4. This circuit may be combined with these circuits as
disclosed herein to provide useful circuit functions.
LCVC circuit 60 of FIG. 6a is similar to the LVCC circuit 10 FIG. 1, except
that the gates of the transistors 12 and 14 are tied to their common drain
connection at output node 18. The input current I.sub.in is supplied to
the drains, and the output voltage V.sub.out is the common drain voltage
of transistors 12 and 14 (i.e., the voltage at node 18).
Kirchoff's current law requires that the current going into the drains of
transistors 12 and 14 equal the current flowing out of the drains of those
transistors. At steady state, the output voltage V.sub.out should cause
the two transistors 12 and 14 to supply enough current to balance the
input current I.sub.in. When the size ratio of MOS transistors 12 and 14
is correctly selected, the current supplied by MOS transistors 12 and 14
is a linear function of the gate voltage, and the output voltage is a
linear function of the input current I.sub.in.
The transfer function of the LCVC circuit of FIG. 6a is shown in FIG. 7.
The different curves of FIG. 7 depict the transfer function for different
values of V.sub.L.
When both transistors are above threshold and in saturation, the equation
describing current balance for the LCVC circuit 60 of FIG. 6a is:
##EQU8##
When the sizes of transistors 12 and 14 satisfy equation (2), then the
quadratic terms involving V.sub.out cancel, yielding a linear transfer
function:
##EQU9##
Equation (17) is valid whenever both transistors are operating in a region
above threshold. Because both transistors are diode-connected, they are
always in saturation. Therefore, the LCVC circuit 60 of FIG. 6a is useful
when:
V.sub.L +V.sub.T.sub.n <V.sub.out <V.sub.H +V.sub.T.sub.p (18)
Referring now to FIG. 6b, another embodiment of a LCVC circuit according to
the present invention is shown. The circuit is identical to the LCVC
circuit of FIG. 6a with the addition of diode connected P-channel MOS
transistor 13 between the source of P-channel transistor 12 and its
voltage rail 20 and diode connected N-channel MOS transistor 15 between
the source of N-channel transistor 14 and its voltage rail 22. The circuit
of FIG. 6b has some advantages over the circuit of FIG. 6a in that it
shows linear behavior over a wider range of input current range for a
given current through the transistors. If sufficient power supply voltage
is available, those of ordinary skill in the art will readily see that
additional diode connected transistors may be added to achieve an even
wider current range over which linear behavior will be exhibited.
From the disclosure herein, those skilled in the art can readily appreciate
that the LCVC and LVCC circuits 10 and 60 and variations disclosed herein
can be connected together in various ways, to yield various combinations
of mirroring and inverting functions. The present invention includes these
combinations. Several examples of more complex circuit systems according
to the present invention will now be disclosed.
Referring now to FIG. 8a, one useful circuit which may be configured
according to the present invention from combinations of the circuits
disclosed herein is an current negator (CN) circuit. A current negator
circuit in its basic form according to the present invention supplies an
output current equal in magnitude and opposite in sign to an input
current.
A CN circuit 70 according to the present invention, shown in block form in
FIG. 8a, is a combination of the LCVC circuit 60 of FIG. 6a or 6b driving
the LVCC circuit 10 of FIG. 1a or 1b. The output of the LCVC circuit 60 is
the input to the LVCC circuit 10. The input current I.sub.in of the CN
circuit 70 is the input to the LVCC portion 60 of the circuit. The output
I.sub.out of the CN circuit 70 is the output current of the LVCC portion
10 of the circuit.
Referring to FIG. 8b in first particular embodiment of a CN circuit
according to the present invention, CN circuit 70 includes four MOS
transistors, one P-channel transistor 72 and one N-channel transistor 74
in the input section and one P-channel transistor 76 and one N-channel
transistor 78 in the output section. An input current I.sub.in is applied
from an input node 80 to the gates of both transistors 72 and 74, which
are connected together. The drains of transistors 72 and 74 are connected
together to form an intermediate node 82. The intermediate node 82 is
connected to the input node 80. The source of the P-channel transistor 72
is connected to a first input voltage rail 84 having a first voltage
potential V.sub.Hin, and the source of the N-channel transistor 74 is
connected to a second input voltage fail 86 having a second lower voltage
potential V.sub.Lin.
Intermediate node 82 is connected to the gates of P-channel channel
transistor 76 and N-channel transistor 78. The drains of P-channel and
N-channel transistors 76 and 78 are connected together to output node 88.
The source of the P-channel transistor 76 is connected to a fist output
voltage rail 90 having a first voltage potential V.sub.Hout, and the
source o the N-channel transistor 78 si connected to a second output
voltage rail 92 having a second voltage potential V.sub.Lout, more
negative than V.sub.H.
The output current I.sub.out is the negation of the input current I.sub.in,
i.e. I.sub.out =-I.sub.in, when the transistors of the LCVC portion of the
circuit are matched in size to the corresponding transistors of the LVCC
portion of the circuit, when the voltages V.sub.H and V.sub.L on the
voltage rails of the LCVC portion of the circuit are the same as those of
the LVCC portion of the circuit and when the transistors of he LVCC
portion of the circuit are in saturation:
V.sub.in -V.sub.T74 <V.sub.out <V.sub.in -V.sub.T72 (19)
Those of ordinary skill in the art wiml recognize that the LVCC circuit 10
and he LCVC circuit 60 of the CN circuit do not have to be operated above
threshold because any non-linearity int eh LCVC portion of the circuit
will be cancelled by an equivalent non-linearity in the LVCC portion of
the circuit.
The CN circuit 70 of the present invention may also be considered to be a
pair of current mirrors, one P-channel and one N-channel, sharing the same
input and output nodes. Such a pair of current mirrors is depicted in
block from in FIG. 8c. One embodiment of the P-channel mirror 94 is
transistors 72 and 76 of FIG. 8b. Similarly, on embodiment of the
N-channel current mirror 96 is transistors 74 and 78 of FIG. 8b.
The graph of FIG. 9 illustrates the transfer curves for the CN circuit 70
shown in FIG. 8b.
Those of ordinary skill in the art will appreciate that different current
mirrors can be substituted for the standard current mirrors used in the
circuit of FIG. 8b. Examples of such variations of the present invention
are depicted in FIGS. 8d-8g. Referring now to FIG. 8d, a CN circuit
according to the present invention includes a pair of Wilson current
mirrors. P-channel transistors 100, 102 and 104 form a P-channel current
mirror having an input node 106 and an output node 108. N-channel
transistors 110, 112, and 114 form a N-channel current mirror sharing
input node 106 and output node 108.
Referring now to FIG. 8e, an alternate embodiment of a CN circuit according
to the present invention includes a pair of cascode current mirrors.
P-channel transistors 116, 118, 120 and 122 format P-channel current
mirror having an input node 106 and an output node 108. N-channel
transistors 124, 126, 128 and 130 form an N-channel current mirror sharing
input node 106 and output node 108 with the P-channel current mirror.
Referring now to FIG. 8f, another alternate embodiment of a CN circuit
according o the present invention includes a pair of multiple stage Wilson
current mirrors. P-channel transistors 132, 134, 136, and 138 form a
multiple Stage P-channel current mirror having an input node 106 and an
output node 108. N-channel transistors 140, 142, 144, and 146 form an
N-channel current mirror sharing input node 106 and output node 108 with
the P-channel current mirror.
Referring now to FIG. 8g, yet another CN circuit according to the present
invention includes a pair of multiple stage cascode current mirrors.
P-channel transistors 150, 152, 154, 158, 158 and 160 form a multiple
stage P-channel current mirror having an input node 106 and an output node
108. N-channel transistors 162, 164, 166, 168, 170, and 172 form an
N-channel current mirror sharing input node 106 and output node 108 with
the P-channel current mirror.
The circuits in FIGS. 8d-8g offer some advantages over the circuit of FIG.
8b. The output impedances of the circuits of FIGS. 8d-8g are much higher
than the output impedance of the circuit of FIG. 8b. Therefore, the output
portions of the circuits of FIGS. 8d-8g are more like pure current sources
than is the output portion of the circuit of FIG. 8b. Furthermore, like
the circuit in FIG. 8b, the circuits of FIGS. 8d-8g can be extended to
have more than one output stage.
Those of ordinary skill in the art will recognize that the examples given
herein are illustrative only and that, for purposes of the present
invention, two uni-directional current mirrors of any type can be
connected together to form a CN circuit, as long as one current mirror is
made using n-type transistors and the other current mirror is made using
p-type transistors.
There are two ways that the CN circuits of the present invention can be
made to have a current gain having a magnitude other than unity. First,
the strengths of the transistors in the LVCC circuit can be made different
from the strengths of the transistors in the LCVC circuit. The strength of
a transistor is the ratio of its width to its length. When the strengths
of the transistors are different, the CN circuit will be functional when
the output transistors are in saturation. The current gain of the CN
circuit is equal to the transistor strength ratio between the transistors
in the LVCC circuit and the transistors in the LCVC circuit. This
technique applies to the CN circuit of FIG. 8b.
The circuits of FIGS. 8d, 8e and 8g can also be made to have a current gain
other than unity, by using a constant strength ratio between all of the
transistors in the output stage and all of the transistors in the input
stage.
A second way to obtain a current gain having a magnitude other than unity
for the CN circuit shown in FIGS. 8b is to make the rail voltages V.sub.H
and V.sub.L of the LVCC circuit portion different from the rail voltages
V.sub.H and V.sub.L of the LCVC circuit portion. Under this circumstance,
both the LCVC circuit 60 and the LVCC circuit 10 should be operated in
their operating regimes as previously described herein. The current gain
of the CN circuit of FIG. 8b is:
##EQU10##
where, r is the transistor strength ratio between the transistors of the
LVCC circuit 10 and the LCVC circuit 60. If a zero output current is
desired when a zero input current is applied to the circuit, then the
following condition should be met:
V.sub.H.sub.in +V.sub.L.sub.in +V.sub.T.sub.92 +V.sub.T.sub.94
=V.sub.H.sub.out +V.sub.L.sub.out +V.sub.T.sub.96 +V.sub.T.sub.98 (21)
Like conventional current mirror circuits from which they are made, the CN
circuits of the present invention, including those depicted in FIGS. 8a,
8b, 8c and 8g-8g may be configured to have more than one output by
connecting more than one output stage to the appropriate node or nodes of
the input stage.
Referring now to FIG. 10a, a schematic diagram an N-output scaleable CN
circuit according to the present invention is shown. Using the reference
numerals from FIG. 8c, it may be seen that both the P-channel and the
N-channel current mirrors may be conceptually divided into input sections
94.sub.i and 96.sub.1, and output sections 94.sub.out1 -94.sub.outn and
96.sub.out1 -94.sub.outn. Corresponding output sections are connected
together to form output nodes I.sub.out1, I.sub.out2, and I.sub.outn. Each
output section may be tailored to have a current gain of other than one in
the manner taught for the embodiment shown in FIG. 8b.
As an example of the provision of multiple outputs in the CN circuits
according to the present invention, FIG. 10b shows additional outputs
provided to the CN circuits of FIG. 8b. The input stage of the CN circuit
is formed from P-channel transistor 72 and N-channel transistor 74,
connected to input node 80 and voltage rails 84 and 86 as shown in and
described with reference to FIG. 8b.
A desired number of output stages may be connected to intermediate node 82.
As shown in FIG. 10b, three illustrative output stages are connected to
intermediate node 82. The first includes P-channel transistor 76a,
connected to N-channel transistor 78a and to output node 88a and to
voltage rails 90a and 92 a in the manner described with respect to FIG.
8b. The second includes P-channel transistor 76b, connected to N-channel
transistor 78b and to output node 88b and to voltage rails 90b and 92b in
the same manner. The third includes P-channel transistor 76n, connected to
N-channel transistor 78n and to output node 88n and to voltage rails 90n
and 92n also in the manner described with respect to FIG. 8b.
The multiple output CN circuits of the present invention may be tailored to
have different current gains in the manner taught therein with respect to
the single output versions. For instance, those of ordinary skill in the
art will appreciate that, by adjusting the transistor strength ratios or
by properly choosing voltages for voltage rails 90a-c and 92a-c, output
nodes 88a-c may be caused to produce currents of magnitudes of other than
-1x I.sub.in.
Another useful circuit realized by combining the circuits disclosed herein
is a voltage negator circuit, which is a combination of the LVCC circuit
10 of FIG. 1a or 1b driving the LCVC circuit 60 of FIG. 6a or 6b. An
example of such a circuit is shown in FIG. 11a. Voltage negator circuit
180 includes LVCC circuit 10 followed by LCVC circuit 60.
A particular embodiment of voltage negator circuit 178 is shown in FIG. 11b
and includes four MOS transistors, one P-channel transistor 182 and one
N-channel transistor 184 in the input section and one P-channel transistor
186 and one N-channel transistor 188 in the output section. An input
voltage V.sub.in is applied from an input node 190 to the gates of both
transistors 182 and 184, which are connected together. The drains of
transistors 182 and 184 are connected together to form an intermediate
node 192. The source of the P-channel transistor 182 is connected to a
first input voltage rail 194 having a first voltage potential V.sub.Hin,
and the source of the N-channel transistor 194 is connected to a second
input voltage rail 196 having a second lower voltage potential V.sub.Lin.
Intermediate node 192 is connected to the gates of P-channel transistor 186
and N-channel transistor 188. The drains of P-channel and N-channel
transistors 186 and 188 are connected together to output node 198 as well
as to intermediate node 192. The source of the P-channel transistor 186 is
connected to a first output voltage rail 200 having a first voltage
potential V.sub.Hout, and the source of the N-channel transistor 188 is
connected to a second output voltage rail 202 having a second lower
voltage potential V.sub.Lout.
The voltage negator circuit of FIG. 11b is functional when the LVCC circuit
and LVCC circuit portions of the voltage negator are in their functional
regimes as described previously herein. The transfer function for the
voltage negator circuit of FIG. 11b is shown in FIG. 12.
There are two ways in which the voltage negator circuit of FIGS. 11a and
11b may have a voltage gain different from one. First, the strengths of
the transistors in the LVCC circuit portion of the voltage negator can be
made different from the strengths of the transistors in the LCVC circuit
portion. The voltage gain of the voltage negator circuit of FIGS. 11a and
11b is the negative of the ratio of transistor strengths between the LVCC
circuit portion and the LCVC circuit portion.
Second, the voltages V.sub.H and V.sub.L on the voltage rails of the LVCC
circuit portion may be made different from the voltages V.sub.H and
V.sub.L on the voltage rails of the LVCC circuit portion of the circuit.
The voltage gain of the circuit is:
##EQU11##
where r is the transistor strength ratio between the LVCC portion and the
LCVC circuit portion of the voltage negator circuit and the subscript
numbers correspond to the reference numbers of the various transistors in
the circuit.
An non-inverting linear voltage-to-current converter (ILVCC) circuit may be
provided according to the present invention by combining a LVCC circuit of
FIG. 1a as an input and a CN circuit of any one of FIGS. 8a-8e as an
output. Such a combination is shown in block diagram form in FIG. 13. The
output of the LVCC circuit is connected to the input of the CN circuit.
The output current of the NLVCC circuit is linearly related to its input
current, with the sign opposite to that of an LVCC circuit.
The principles and circuits of the present invention may be used to provide
a delay line. Such a circuit is shown in block form in FIG. 14. A delay
line 120 according to a presently preferred embodiment of the invention
includes a chain of voltage negator circuits 90, like that of FIG. 11a,
connected in cascade, with capacitor 122 on the output of each voltage
negator circuit 90. A delayed version of the original signal appears on
the output of every even voltage negator circuit 90 in delay line 120 and
a delayed version of the inverted signal appears on the output of every
odd voltage negator circuit 90 in delay line 120. Those of ordinary skill
in the art will recognize that an arbitrary number of voltage negator
circuits 90 may be used, depending on the delay desired, possibly subject
to bandwidth limitations as described on page 154 of the book Analog VLSI
and Neural Systems. The delay can be adjusted by adjusting V.sub.H
-V.sub.L, and the gain can be adjusted by making V.sub.H and V.sub.L of
the input sections of the voltage negator circuit slightly different from
the V.sub.H and V.sub.L of the output sections.
A linear neuron according to another aspect of the present invention may be
fabricated from a plurality of LCTM circuits 32 (FIG. 4) and one LCVC
circuit 50 (FIG. 6) as shown in FIG. 15. If x.sub.i is defined as V.sub.xi
-V.sub.xo and y.sub.i is defined as V.sub.yi -V.sub.yo, where V.sub.xi are
the V.sub.x inputs of a plurality of LCTM circuits 32, V.sub.yi are the
V.sub.y inputs o the LCTM circuits, and where V.sub.xo and V.sub.yo are as
previously defined herein, then the outputs of a plurality of LCTM
circuits 32 are the dot products of the terms x.sub.i and y.sub.i.
Because they are currents, he outputs of the LCTM circuits may be summed on
a single wire. These outputs may be connected together to the input of the
LCVC circuit 50 since its current driven input inherently sums the current
components at its input node. The output voltage V.sub.out of the LVCC
circuit of the linear neuron may be expressed as:
##EQU12##
and is the dot produce of the vectors x.sub.i and y.sub.i, where i=o to n.
The principles and circuits of the present invention may also be used to
provide a current sense amplifier. A current sense amplifier circuit 210
according to the present invention is shown in FIG. 16. A bi-directional
current input, shown as a current source 132, is connected to node 134,
the non-inverting input node of amplifier 136. Amplifier 136 may be one of
a variety of available amplifier circuits, such as the one described in
Analog VLSI and Neural Systems, p. 70, preferably having a voltage gain
much larger than one. The inverting input node 138 to amplifier 136 is
connected to a reference voltage V.sub.ref. A LVCC circuit 140, such as
that shown in FIGS. 1a and 1b is placed in a feedback path from the output
of amplifier -36 to its non-inverting input node 134. The input to the
LVCC circuit 140 and the output of the current sense amplifier 130 is
output 142 of amplifier 136.
The purpose of the circuit 130 is to hold non-inverting input node 134 at
the same voltage as inverting input node 138 of the amplifier 136, and to
generate an output voltage at output node 142 which is a linear function
of the current provided by the input current source 132.
The sense amplifier of FIG. 16 is linear because the LVCC circuit 138 is
linear. A change in the output voltage at output node 142 will cause a
proportional change in the output current of the LVCC.
In order to make the circuit more stable, a compensation capacitor 146 may
be connected between non-inverting input node 132 and the output of
transconductance amplifier 136. Those of ordinary skill in the art can
adjust the output impedance of amplifier 136, the transconductance of the
LVCC circuit -40, and the compensation capacitor 146 in order to yield
desired speed and phase margin for the whole current sense amplifier 130.
The LVCC circuit 140 is kept in its operating range by choice of reference
voltage at inverting input node 138 of transconductance amplifier 136,
which constrains the voltage on node 132, and, when given a range of input
current, by choice of the transconductance of the LVCC circuit 140, which
constrains the voltage on the output of transconductance amplifier 136.
While a presently-preferred embodiment of the invention has been disclosed,
from an examination of the within disclosure and drawings, those of
ordinary skill in the art will be able to configure other embodiments of
the invention. These other embodiments are intended to fall within the
scope of the present invention which is to be limited only by the scope of
the appended claims.
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