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| United States Patent |
5,075,576
|
|
Cavlan
|
*
December 24, 1991
|
Field-programmable logic device with programmable foldback to control
number of logic levels
Abstract
A monolithic integrated circuit contains a field-programmable logic
architecture centered on a single array of programmable gates that perform
either logical NAND or logical NOR operations. Foldback loops can be
readily programmed through the array to enable the user to achieve
different numbers of logic levels.
| Inventors:
|
Cavlan; Napoleone (Cupertino, CA)
|
| Assignee:
|
North American Philips Corporation (Sunnyvale, CA)
|
| [*] Notice: |
The portion of the term of this patent subsequent to October 27, 2004
has been disclaimed. |
| Appl. No.:
|
642655 |
| Filed:
|
December 3, 1990 |
| Current U.S. Class: |
326/39; 326/38; 326/52; 326/54; 326/95; 327/197; 708/232 |
| Intern'l Class: |
H03K 019/12; H03K 017/16 |
| Field of Search: |
307/443,480,465-469,202.1,272 R,471,272 A
364/716
|
References Cited
U.S. Patent Documents
| 4157480 | Jun., 1979 | Edwards | 307/465.
|
| 4384737 | Sep., 1982 | Cukier et al. | 364/716.
|
| 4422072 | Dec., 1983 | Cavlan | 307/465.
|
| 4488230 | Dec., 1984 | Harrison | 364/716.
|
| 4501977 | Feb., 1985 | Koike | 364/716.
|
| 4516040 | May., 1985 | Zapisek et al. | 364/716.
|
| 4562427 | Dec., 1985 | Ecton | 307/465.
|
| Foreign Patent Documents |
| 0170122 | Oct., 1983 | JP | 307/465.
|
Other References
Radcliffe, "Fusable Diode Array Circuits", IBM T.D.B., vol. 21, No. 1, Jun.
1978, pp. 105-108.
|
Primary Examiner: Miller; Stanley D.
Assistant Examiner: Wambach; Margaret Rose
Attorney, Agent or Firm: Tamoshunas; A., Haken; J., Meetin; R.
Parent Case Text
CROSS REFERENCE TO RELATED APPLICATIONS
This is a continuation of U.S. patent application Ser. No. 085,917, filed
Aug. 17, 1987, now abandoned, which is a division of U.S. patent
application Ser. No. 799,676, filed Nov. 19, 1985, now U.S. Pat. No.
4,703,206.
Claims
I claim:
1. A monolithic integrated circuit containing a programmable logic device
that comprises:
a plurality of primary lines, part of which are input lines for receiving
internal input data and part of which are foldback lines;
an array of primary logic gates, each gate having (1) a plurality of input
sections of which each is connected to a different one of the primary
lines and (2) an output section for providing an output signal as either
the logical NAND or the logical NOR of the input data to that gate, at
least part of the gates being foldback gates corresponding on a one-to-one
basis of the foldback lines;
means for selectively programmably connecting each input section of each
primary gate to its output section; and
foldback means that permanently and non-programmably couple the output
section of each foldback gate to the corresponding foldback line so that
each foldback line receives a signal of the same logical value as the
output signal of the corresponding foldback gate.
2. An integrated circuit as in claim 1 wherein the circuit has pins for
receiving circuit input data and supplying circuit output data, the device
including:
input means for performing at least one digital operation on at least part
of the circuit input data to generate at least part of the internal input
data; and
output means for performing at least one digital operation on the output
signal from at least one of the gates to generate at least part of the
circuit output data.
3. An integrated circuit as in claim 2 wherein the device further includes
internal means for performing at least one digital operation on the output
signal form at least one of the gates to generate internal device data and
for supplying it to at least one of the primary lines exclusive of the
input and foldback lines.
4. An integrated circuit as in claim 2 wherein the output means comprises
means for supplying one of the pins with a signal that is either logically
the same as or logically inverse to the output signal from one of the
gates.
5. An integrated circuit as in claim 4 wherein activation of the means for
supplying is under control of the output signal from another of the gates.
6. An integrated circuit as in claim 1 wherein each foldback gate has its
input sections respectively connected either to all of the primary lines
or to all of the primary lines except its own foldback line.
7. An integrated circuit as in claim 6 wherein the means for connecting
comprises a group of field-programmable elements.
8. An integrated circuit as in claim 7 wherein the primary gates are all
NAND gates.
9. An integrated circuit as in claim 7 wherein the primary gates are all
NOR gates.
10. An integrated circuit as in claim 1 wherein the foldback means
comprises, for each foldback line, a direct connection of that line to the
output section of the corresponding foldback gate so as to receive its
output signal.
11. An integrated circuit as in claim 1 including a further gate for
generating an output signal as either the EXCLUSIVE OR or the EXCLUSIVE
NOR of the output signal from one of the primary gates and a signal which
is programmably either logical "0" or "1".
12. An integrated circuit as in claim 11 further including means for
generating an output signal which is either logically the same as or
logically inverse to the output signal from the further gate, activation
of the means for generating being under control of the output signal form
another of the primary gates.
13. An integrated circuit as in claim 1 including a further gate for
generating an output signal as either the EXCLUSIVE OR or the EXCLUSIVE
NOR of the output signals from a pair of the primary gates.
14. An integrated circuit as in claim 13 further including means for
generating an output signal which is either logically the same as or
logically inverse to the output signal from the further gate, activation
of the means for generating being under control of the output signal from
another of the primary gates.
15. An integrated circuit as in claim 1 including a flip-flop responsive to
at least one data input signal for generating an output signal, each data
input signal being either logically the same as or logically inverse to
the output signal from a corresponding one of the gates.
16. An integrated circuit as in claim 15 wherein the flip-flop is also
responsive to a clock signal, the output signal of the flip-flop being
generated in synchronism with the clock signal.
17. An integrated circuit as in claim 16 wherein one of the primary lines
exclusive of the input and foldback lines receives data which is either
logically the same as or logically inverse to the output signal of the
flip-flop.
18. An integrated circuit as in claim 1 including means for generating a
signal that is either logically the same as or logically inverse to the
output signal from one of the gates, activation of the means for
generating being under control of the output signal from another of the
gates.
Description
FIELD OF USE
This invention relates generally to digital integrated circuits and, in
particular, to programmable logic devices.
BACKGROUND ART
Programmable logic devices have become popular in the electronics industry
because they allow the manufacturer and user flexibility in tailoring a
general integrated circuit to meet specific application at low cost.
Programmable logic devices are generally classified as field-programmable
and mask-programmable. In contrast to a mask-programmable logic devices
which the manufacturer programs late in the fabrication process and then
distributes to the customer, a field-programmable logic device (hereafter
generally "PLD") is typically distributed in an unprogrammed state. The
customer subsequently programs the PLD to perform a desired logic
function.
Logical operations in PLD's are performed with arrays of basic logic gates
having programmable elements at selected points. The most common type of
programmable element is a fusible link or fuse. A PLD is programmable to
imbed a particular function in the device by destroying (or "blowing") a
specific pattern of the fuses. Blowing a fuse creates an open circuit at a
location where an electrical connection is not wanted. Conversely, a
closed circuit exists at a crosspoint where the fuse remains intact to
provide an electrical connection. Another type of programmable element is
the so-called "antifuse". In contrast to a fuse, an antifuse is initially
an open circuit and is programmed to create a closed circuit where an
electrical connection is desired.
Turning to the drawings, FIG. 1a illustrates the internal construction of a
conventional unprogrammed logical NAND gate C suitable for a PLD using
fuses as the programmable elements. Digital input data consisting of N
input signals V.sub.Il -V.sub.IN is provided from primary lines L.sub.l
-L.sub.N to N corresponding input sections of gate C. Letting J be a
running integer, each gate input section consists of a Schottky diode
D.sub.J connected by way of a gate input line S.sub.J to primary line
L.sub.J. A fuse F.sub.CJ couples line S.sub.J (and diode D.sub.J) in the
input section to a line S.sub.C in the output section of gate C. An
inverter N.sub.C connected to line S.sub.C supplies the gate output signal
V.sub.O.
Programming involves destroying certain of fuses F.sub.Cl -F.sub.CN to
disconnect the corresponding input sections of gate C from its output
sections. Signal V.sub.O then becomes the logical NAND of only those of
signals V.sub.Il -V.sub.IN associated with the fuses that are still
intact.
FIG. 1b represents gate C in standard logic notation. This notation is
inconvenient for PLD's. The simplified notation of FIG. 1c alleviates this
problem. In FIG. 1c, line S.sub.C in the output section crosses each line
L.sub.J perpendicularly. Each of the resulting intersections represents
the unprogrammed location for a potential coupling of line S.sub.C to line
L.sub.J through fuse F.sub.CJ (and diode D.sub.J) as shown in FIG. 1a.
Each unprogrammed intersection is marked with a small circle to
distinguish intersections for programmable elements from other circuit
intersections not intended to represent programmable elements. The NAND
symbol (which encompasses only the gate output section here) is placed at
a suitable location along line S.sub.C to indicate the function of the
circuitry. The same notation would be used in FIG. 1c if the programmable
element were an antifuse instead of a fuse.
FIGS. 2a, 2b, and 2c respectively show the internal circuitry of a
conventional unprogrammed logical NOR gate E, its representation in
standard logic notation, and its representation in the simplified notation
described above. As with gate C, signals V.sub.Il -V.sub.IN are provided
from input lines L.sub.l -L.sub.N to N input sections of gate E. Each
input section consists of an NPN transistor Q.sub.J whose base is
connected via a gate input line S.sub.J to line L.sub.J as indicated in
FIG. 2a. A fuse F.sub.EJ connects the Q.sub.J emitter to a line S.sub.E in
the gate output section. Gate output signal V.sub.O is provided from an
inverter N.sub.E connected to line S.sub.E.
Gate E is utilized in the same way as gate C. Selectively blowing fuses
F.sub.El -F.sub.EN causes signal V.sub.O to become the logical NOR of only
those of signals V.sub.Il -V.sub.IN whose fuses remain intact. Likewise,
the simplified notation of FIG. 2c is more appropriate to PLD's than the
standard notation of FIG. 2b. Each circled intersection in FIG. 2c
represents the unprogrammed location for a potential coupling of line
S.sub.E to line L.sub.J through fuse F.sub.EJ.
The preceding remarks also apply to logical AND and logical OR gates.
Replacing inverter N.sub.C in gate C with a non-inverting buffer (or
simply taking the output signal directly from line S.sub.C) transforms the
gate into a programmable AND gate. The same thing can be done with gate E
to convert it into an OR gate.
It is difficult to adjust the number of basic (or Boolean) logic levels in
prior art PLD's. Many simply have fixed numbers of logic levels. Typical
of the fixed-level PLD's are the 82S100, 82S103, and 82S105 integrated
circuits made by Signetics Corporation. The 82S100 and 82S105 have two
levels of Boolean logic. The 82S103 is a single-level device.
FIG. 3a shows the architecture for the 82S100. Circuit input data is
transmitted through M input pins I.sub.l -I.sub.M to complementary-output
buffers W.sub.l -W.sub.M which supply the true input data and its
complement to array input lines L.sub.l -L.sub.2M. An array of P
programmable AND gates A.sub.l -A.sub.p ANDs the data on lines L.sub.l
-L.sub.2M to provide a first level of logic as Boolean products. The
second level of logic is to form sums of the products. This is done with a
array of Q programmable OR gates E.sub.l -E.sub.Q that OR the data from
gates A.sub.l -A.sub.p. EXCLUSIVE OR gates X.sub.l -X.sub.Q selectively
invert the ORed data. The resulting data is supplied through buffers
B.sub.l -B.sub.Q, whose activation can be externally controlled, to output
pins O.sub.l -O.sub.Q.
The 82S103 is similar to the 82S100 except that the 82S103 does not have
the OR logic level. Also, the AND array is replaced with an array of
programmable NAND gates, each arranged as described in FIG. 1a. The NAND
gates are directly connected to the EXCLUSIVE OR gates.
FIG. 3b shows the basic building blocks of the 82S105. In this simplified
representation, gates A.sub.l -A.sub.p AND the data on input lines L.sub.l
-L.sub.2M and on typical feedback lines L.sub.E1, L.sub.E2, and L.sub.N.
The ANDed data is supplied to typical gates E.sub.l -E.sub.4 and E.sub.N
in a programmable OR array. SR flip-flops FF.sub.1 and FF.sub.2 provide
on-chip data storage. Their data inputs accept the ORed data from gates
E.sub.1 -E.sub.4 in synchronism with a clock signal V.sub.CK. The
flip-flop states can be set asynchronously to logical "1" through a preset
signal V.sub.P. The FF.sub.1 output data is fed back to the AND array. The
FF.sub.2 output data is supplied via an externally controllable buffer
B.sub.F to a pin O.sub.F. The 82S105 also has a (single) programmable NOR
loop for feeding data complementary to that supplied from gates A.sub.l
-A.sub.p back into them. The NOR loop is formed with an inverter N.sub.N
connected between line L.sub.N and gate E.sub.N.
U.S. Pat. No. 4,422,072 describes more advanced versions of the foregoing
Signetics PLD's. These more advanced versions offer significantly more
architectural flexibility. To a certain degree, they can be programmed to
achieve different numbers of basic logic levels. Since they are basically
directed toward fixed-level usage, this is a relatively tortuous process
which entials sacrificing some of their internal logic resources, package
pins, and performance.
GENERAL DISCLOSURE OF THE INVENTION
The present invention provides a programmable logic architecture centered
on a single programmable logic array that the user can readily configure
in foldback loops to achieve different numbers of Boolean logic levels
within a single integrated circuit. This provides a great increase in
usage efficiency. The array typically serves as a highly flexible central
interconnect system for coupling peripheral logic elements of various
complexity.
In particular, the programmable logic device of the invention employs an
array of primary logic gates that operate on data transmitted on a
plurality of primary lines. Each gate has a plurality of input sections,
each connected to a different one of the primary lines. Each gate also has
an output section for providing an output signal as either the logical
NAND or the logical NOR of the gate input data. The gates have elements
for selectively programmably connecting each input section of each gate to
its output section. One part of the primary lines are array input lines
for receiving external input data to the array. Another part of the
primary lines are foldback lines which are respectively connected to the
output sections of a corresponding part of the gates, referred to as
foldback gates, to receive their output signals.
Insofar as the term "programmably connecting" and similar terms are used
herein, these terms are intended to mean both the situation where the
programmable elements are initially closed circuits that are opened during
programming and the situation in which the programmable elements are
initially open circuits that are closed during programming. That is,
"programmably connecting" covers both fuses and antifuses.
Configuring the present logic device to obtain various numbers of logic
levels simply involves programming the programmable elements located in
the array of gates itself. No other elements need to be programmed.
Consider the preferred case in which all the gates are NAND gates.
According to DeMorgan's theorem, a NAND gate with inverted inputs
functions as an OR gate. If a gate in the present array is programmed to
connect its output section to a pair of its input sections connected to
foldback lines, the resulting foldback loop through that gate and the
corresponding pair of foldback gates yields two levels of NAND logic.
These are equivalent to a level of AND logic followed by a level of OR
logic. More than two logic levels can be attained by programming further
foldback loops through the array. An important feature of the invention is
that different input-to-output paths through the device can be programmed
to have different numbers of basic logic levels. This makes the invention
very adaptable.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS.. 1a, 1b, and 1c respectively show a circuit diagram for a
conventional programmable NAND gate, its standard logic representation,
and its representation in a simplified PLD notation.
FIGS. 2a, 2b, and 2c respectively show a circuit diagram for a conventional
programmable NOR gate, its standard logic representation, and its
representation in the simplified PLD notation.
FIGS. 3a and 3b are circuit diagrams respectively representing two prior
art PLD's.
FIGS. 4 and 5 are circuit diagrams for basic PLD's that respectively use
NAND and NOR arrays with foldback in accordance with the invention.
FIG. 6 is a circuit/block diagram for a multi-capability PLD using the NAND
core of FIG. 4.
FIGS. 7 and 8 are circuit diagrams for particular embodiments of the PLD of
FIG. 6.
Like reference symbols are employed in the drawings and in the description
of the preferred embodiments to represent the same or very similar item or
items. Reference symbols beginning with "I" and "O" respectively indicate
circuit input and output pins. Reference symbols beginning with "V"
indicate signals that are not necessarily transmitted at the input and
output pins.
Each circled intersection in which the vertical (crossing) line is
connected to ground reference but which is located outside the array(s) of
programmable gates indicates a programmable element. By suitably
programming this element, the horizontal (crossing) line is either
grounded at logical "0" or left as an open circuit at logical "1".
DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 4 illustrates a single-chip NAND-based field-programmable logic device
with foldback that can be programmed to achieve different numbers of
levels of logic. This PLD has a group of primary lines consisting of 2M
array input lines L.sub.l -L.sub.2M, R foldback lines L.sub.Al -L.sub.AR,
and S foldback lines L.sub.Bl -L.sub.BS. Input data to the integrated
circuit is transmitted from input pins I.sub.l -I.sub.M to respective
complementary-output buffers W.sub.l -W.sub.M which provide the true input
data and its complement to input lines L.sub.l -L.sub.2M.
The PLD has an array of programmable NAND gates whose input sections are
respectively connected to lines L.sub.l -L.sub.2M, L.sub.Al -L.sub.AR, and
L.sub.Bl -L.sub.BS. Each NAND gate is configured (for example) as shown in
FIG. 1a using fuses for programming. One part of the NAND array consists
of R foldback gates C.sub.Al -C.sub.AR whose output sections respectively
provide their output signals directly to lines L.sub.Al -L.sub.AR. Another
part of the array consists of S foldback gates C.sub.Bl -C.sub.BS whose
output sections are similarly connected respectively to lines L.sub.Bl
-L.sub.BS.
In programming this PLD, the fuses connecting the output sections of each
gate C.sub.AJ or C.sub.BJ (where J is a running integer) to the input
section connected to its foldback line L.sub.AJ or L.sub.BJ must be blown
to create open circuits. This is done to avoid oscillations.
Alternatively, these particular fuses could simply be deleted in
fabricating the array.
The programmable array also includes T gates C.sub.Cl -C.sub.CT. The NAND
output signals from gates C.sub.Bl -C.sub.BS and C.sub.Cl -C.sub.CT are
respectively provided to the first inputs of S EXCLUSIVE OR gates X.sub.Bl
-X.sub.BS and T EXCLUSIVE OR gates X.sub.Cl -X.sub.CT. The second inputs
of gates X.sub.Bl -X.sub.BS and X.sub.Cl -X.sub.CT are programmably
groundable to enable output data from gates C.sub.Bl -C.sub.BS and
C.sub.Cl -C.sub.CT to be selectively inverted. The elements that provide
the programmable grounding are implemented (for example) in the way
described in U.S. Pat. No. 4,422,072, cited above. The output signals from
gates X.sub.Bl -X.sub.BS and X.sub.Cl -X.sub.CT are respectively supplied
to S output pins O.sub.Bl -O.sub.BS and T output pins O.sub.Cl -O.sub.CT.
The PLD has a limited number of pins. Consequently, R is normally chosen to
be much higher than S so as to maximize pin usage efficiency.
Various numbers of Boolean logic levels can be obtained in the PLD by
configuring suitable foldback loops through the NAND array. A foldback
loop is created by programming the array in such a manner that there are
complete electrical paths extending from two or more of the input sections
of each of two or more of the foldback gates--e.g., gates C.sub.A1 and
C.sub.A2 --through their output sections and along their foldback
lines--i.e., lines L.sub.A1 and L.sub.A2 here--to the output section of
another of the gates--e.g., gate C.sub.Cl --by way of its input sections
connected to those foldback lines.
Specifically, the C.sub.Cl fuses "along"--i.e., connected to the gate input
sections connected to--lines L.sub.A1 and L.sub.A2 are allowed to remain
intact. If the user wants gate C.sub.A1 to respond to input data at pins
I.sub.l -I.sub.M, two or more of the C.sub.A1 fuses "along" lines L.sub.l
-L.sub.2M are allowed to remain intact, subject to the proviso that the
C.sub.Al fuse(s) "along" at least one of the two lines extending from the
outputs of each of buffers W.sub.l -W.sub.M must be blown. The same
applies to gate C.sub.A2 if the user wants it to respond to pin input
data.
The result is that gates C.sub.A1 and C.sub.A2 receive array input data
from certain of lines L.sub.l -L.sub.2M to provide a first level of NAND
logic. The output signals from gates C.sub.A1 and C.sub.A2 are supplied as
input signals to gate C.sub.Cl to obtain a second NAND logic level. The
foldback loop formed with gates C.sub.A1, C.sub.A2, and C.sub.Al thereby
gives a two-level NAND-NAND arrangement.
A NAND gate is functionally an AND gate with output inversion. Gates
C.sub.A1 and C.sub.A2 therefore are AND gates with inverters at their
outputs. These inverters can be functionally shifted to the C.sub.Cl
inputs. Under DeMorgan's theorem, a NAND gate with inverted inputs
performs an OR function. Accordingly, the NAND-NAND arrangement formed
with gates C.sub.A1, C.sub.A2, and C.sub.C2 is functionally equivalent to
a two-level AND-OR structure. This gives the standard Boolean sum of
products.
By slightly altering the preceding foldback loop, it can be placed in
series with one or more additional foldback loops to achieve three or more
levels of logic. In particular, the array could be programmed so that
foldback gates C.sub.A1 and C.sub.A2 receive input data from other
foldback gates by way of their foldback lines instead of solely from lines
L.sub.l -L.sub.2M. A three-level arrangement is a NAND-NAND-NAND structure
which is functionally equivalent to an AND-OR-NAND structure (or to a
NAND-AND-OR structure). Similarly, a four-level arrangement is a
NAND-NAND-NAND-NAND structure functionally equivalent to an AND-OR-AND-OR
structure. Of course, a single level of NAND logic is obtained by simply
not programming any foldback loop along an input-to-output path through
the PLD.
Importantly, different numbers of Boolean logic levels can exist on
different input-to-output paths through the PLD. It can thus be readily
adapted to a large variety of applications.
Returning momentarily to gates C.sub.Bl -C.sub.BS, they provide more
flexibility. They are generally interchangeable with foldback gates
C.sub.Al -C.sub.AR and non-foldback gates C.sub.Cl -C.sub.CT. Also, gates
C.sub.Bl -C.sub.BS can be used to supply output data at intermediate logic
levels.
Moving to FIG. 5, it illustrates the building blocks of a NOR-based PLD in
which foldback loops can be programmed to achieve different numbers of
logic levels. The PLD has K input lines L.sub.l -L.sub.K that receive
array input data and a group of foldback lines of which two such lines
L.sub.A and L.sub.B are shown. The core of this PLD is an array of
programmable NOR gates, of which gates E.sub.A, E.sub.B, and E.sub.C are
typical. Each NOR gate is configured (for example) as shown in FIG. 2a.
Gates E.sub.A and E.sub.B are foldback gates whose output sections are
respectively connected to lines L.sub.A and L.sub.B. The gates have input
sections respectively connected to lines L.sub.l -L.sub.K and to the
foldback lines except that gates E.sub.A and E.sub.B are shown here as not
having input sections connected respectively to lines L.sub.A and L.sub.B
since the associated fuses, if present, would have to be destroyed during
programming to prevent oscillations. Gates E.sub.B and E.sub.C provide
array output data.
The PLD of FIG. 5 is utilized in the same way as that of FIG. 4.
Programming this NOR-based PLD in the manner generally described above for
FIG. 4 yields one or more levels of NOR logic. A NOR gate with inverted
inputs performs an AND function under DeMorgan's theorem. For the
two-level case, the resulting NOR-NOR structure is functionally equivalent
to an OR-AND arrangement. This gives a Boolean product of sums.
The basic NAND array with foldback in FIG. 4 serves as a central
interconnect system for a more complex single-chip PLD whose building
blocks are illustrated in FIG. 6. Normally, there are two or more of each
of the elements indicated in FIG. 6. Each of the lines leading to and from
the various "DEVICE" blocks may also be two or more lines.
With the foregoing in mind, the main programmable array consists of NAND
gates C.sub.A -C.sub.F. On a relative scale, the PLD normally has a large
number of foldback gates C.sub.A, C.sub.B, and C.sub.D so as to maximize
usage efficiency.
Input devices 11 and 12 perform logical operations on input data received
at pins I and IO.sub.F of the integrated circuit and provide the resulting
data to the NAND array on lines L.sub.1 -L.sub.3. Output devices 13, 14,
and 15 perform logical operations on the output data from gates C.sub.B,
C.sub.C, and C.sub.F and supply the resulting data to pins O.sub.B,
O.sub.C, and IO.sub.F. Internal devices 16 and 17 perform logical
operations on the data from gates C.sub.D and C.sub.E and provide the
resulting data back to the array. Devices 11-17 can take many forms
including inverters, non-inverting buffers, complementary-output buffers,
flip-flops, EXCLUSIVE OR gates, counters, registers, multiplexers,
decoders, arithmetic logic units, and memories.
The basic advantage of this configuration lies in merging into a single
programmable core both "interconnect" and "logic transform" elements
required to interlace peripheral on-chip devices (or macros) into a
functional whole performing a specific logic algorithm. The core can, in
turn, be fragmented and distributed in an unprecedented way to maximize
the efficient implementation of each signal path linking individual logic
macros on chip.
FIG. 7 shows a preferred embodiment of the PLD of FIG. 6. The integrated
circuit in FIG. 7 is implemented with antifuses. In view of the preceding
material, much of FIG. 7 is self-explanatory. Accordingly, only a brief
discussion is given here of this preferred embodiment.
Devices 11 and 12 are complementary-output buffers W.sub.1 and W.sub.2. In
device 15, a buffer B.sub.F1 controls transmission of the C.sub.F output
signal to pin IO.sub.F. The activation of buffer B.sub.F1 is controlled by
a signal from the output of a buffer B.sub.F2 whose input is programmably
groundable. Permanently enabling buffer B.sub.F1 makes pin IO.sub.F an
output pin and allows the C.sub.F output data to be fed back to buffer
W.sub.2 ; the user should not attempt to employ pin IO.sub.F as an input
pin. Conversely, disabling buffer B.sub.F1 fixes pin IO.sub.F as an input
pin. Buffer B.sub.F1 is enabled when the B.sub.F2 output signal is logical
"1", and vice versa.
Output devices 14.sub.1 and 14.sub.2 are employed with gate C.sub.C1
-C.sub.C5 of the NAND array. Device 14.sub.1 permits or inhibits
transmission of the C.sub.C1 output data to a pin O.sub.C1 as a function
of the C.sub.C2 output data. This is done with a buffer B.sub.C1 which
lies in the C.sub.C1 output signal path and whose activation is controlled
by the C.sub.C2 output signal. Device 14.sub.2 similarly controls
transmission of the EXCLUSIVE OR of the C.sub.C3 and C.sub.C4 output data
to a pin O.sub.C2. To perform this function, a gate X.sub.C1 generates the
EXCLUSIVE OR of the C.sub.C3 and C.sub.C4 output signals. A buffer
B.sub.C2, whose activation is under control of the C.sub.C5 output signal,
controls transmission of the X.sub.C1 output data to pin O.sub.C2. Buffers
B.sub.C1 and B.sub.C2 are enabled when the respective output signals from
gates C.sub.C2 and C.sub.C5 are logical "0", and vice versa.
The PLD of FIG. 7 preferably has 80 gates C.sub.A. This provides an
extensive foldback capability. There are 24 devices 11. The PLD has 8
combinations of devices 12 and 15. The PLD also contains 4 devices
14.sub.1, 4 devices of the same type in which buffer B.sub.C1 is replaced
with an inverter, and 8 devices 14.sub.2.
FIG. 8 illustrates another preferred embodiment of FIG. 6. This integrated
circuit is implemented with fuses. Only a brief discussion is given here
of FIG. 8 since much of it is self-explanatory.
NAND gates C.sub.C6 and C.sub.C7 are employed with an output device
14.sub.3. It controls transmission of either the C.sub.C6 true output data
or its inverse as a function of the C.sub.C7 output signal. This is
accomplished with a gate X.sub.C2 that generates the EXCLUSIVE OR of the
inverse of the C.sub.C6 output signal and another signal which is
programmably either logical "0" or "1". A buffer B.sub.C3, whose
activation is controlled by the C.sub.C7 output signal, controls
transmission of the X.sub.C2 output signal to pin O.sub.C3. Buffer
B.sub.C3 is enabled when C.sub.CT output signal is logical "0", and vice
versa.
NAND gates C.sub.El -C.sub.E7 are used with internal devices 17.sub.1
-17.sub.3 to provide on-chip data storage. Device 17.sub.1 consists of a
D-type flip-flop F.sub.E1 which supplies its true and complementary output
signals on lines L.sub.El and L.sub.E2 in response to a data input signal
from gate C.sub.El in synchronism with a clock signal. Device 17.sub.2
consists of an SR flip-flop F.sub.E2 which supplies its true and
complementary output signals on lines L.sub.E3 and L.sub.E4 in response to
data input signals from gates C.sub.E3 and C.sub.E4 in synchronism with a
clock signal. Flip-flops F.sub.E1 and F.sub.E2 can be cleared
asynchronously to logical "0" in response to the respective output signals
from gates C.sub.E2 and C.sub.E5. Clearing occurs when the C.sub.E2 and
C.sub.E5 output signals are logical "0", and vice versa.
Device 17.sub.3 controls the clocking of flip-flops F.sub.E1 and F.sub.E2
with an array of further programmable NAND gates C.sub.CK1 and C.sub.CK2
whose output signals are the respective flip-flop clock signals. The input
sections of each gate C.sub.CK1 or C.sub.CK2 are respectively connected to
clock lines L.sub.CK1 -L.sub.CK3 and to lines L.sub.E1 -L.sub.E4. Lines
L.sub.CK1 -L.sub.CK3 respectively transmit the inverse of C.sub.E6 output
signal, the C.sub.E7 output signal, and the inverse of a clocking signal
supplied at a pin ICK.
The PLD of FIG. 8 preferably contains 68 foldback gates C.sub.A. It has 20
devices 11 and 8 combinations 12/15. There are 4 devices 14.sub.1, 4 like
devices with output inversion, and 8 devices 14.sub.3. The PLD also has 8
devices 17.sub.1 and 8 devices 17.sub.2. There is only one gate C.sub.E2
or C.sub.E5 for controlling all 8 flip-flops F.sub.E1 or F.sub.E2. Device
17.sub.3 contains 8 gates C.sub.CK1, 8 gates C.sub.CK2, 4 NCK/W.sub.3
combinations, 2 gates C.sub.E6, and 2 gates C.sub.E7.
While the invention has been described with reference to particular
embodiments, this description is solely for the purpose of illustration
and is not to be construed as limiting the scope of the invention claimed
below. For example, the positions of the diode and the fuse in each of the
input sections of the NAND gate of FIG. 1a could be reversed; each input
section would then consist only of the gate input line. The same thing
applies to FIG. 2a. The NAND and NOR gates could be implemented with
elements other than diodes and bipolar transistors. EXCLUSIVE NOR gates
can generally be substituted for EXCLUSIVE OR gates. Programming could be
done with masks. Thus, various modifications, changes, and applications
may be made by those skilled in the art without departing from the true
scope and spirit of the invention as defined by the appended claims.
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