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United States Patent | 5,047,989 |
Canepa ,   et al. | September 10, 1991 |
An EPROM includes an on chip circuitry for selecting an alternative chapter mode addressing scheme. By utilizing the chapter addressing mode, a plurality of devices can be coupled in parallel, wherein each device is treated as a chapter of the total memory capacity. Hard latches are used to store a designated code and soft latches are used to latch in chapter addresses from data lines. A chapter is evaluated if values stored in the hard latch match the values inputted to the soft latch.
Inventors: | Canepa; George R. (Folsom, CA); Bauer; Mark (Folsom, CA); Kliza; Phil (Folsom, CA) |
Assignee: | Intel Corporation (Santa Clara, CA) |
Appl. No.: | 321909 |
Filed: | March 10, 1989 |
Current U.S. Class: | 365/238.5; 365/185.01; 365/230.03; 365/230.08; 711/117; 711/173 |
Intern'l Class: | G11C 008/00; G06F 012/06 |
Field of Search: | 365/189.02,189.03,189.05,189.07,230.03,230.02,230.08,238.05,189.01,195 |
4368515 | Jan., 1983 | Nielsen | 364/200. |
4685084 | Aug., 1987 | Canepa | 365/230. |
4719598 | Jan., 1988 | Stockton | 365/189. |
4864542 | Oct., 1989 | Oshima et al. | 235/382. |