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United States Patent | 5,045,999 |
Danilenko ,   et al. | September 3, 1991 |
A multi-function high speed sequencer is provided in a high speed instruction processor. The high speed sequencer comprises a first input latch coupled to logic signals for producing a first sequence signal. A chain of alternately clocked even and odd principal latches are coupled to the output of the first input latch to produce even and odd principal sequence signals for accessing a high speed MSU. A plurality of staging latches are coupled between the odd and the even principal latches for producing even and odd secondary sequence signals for accessing a slower speed MSU.
Inventors: | Danilenko; Michael (West Saint Paul, MN); Tanglin; David J. (Anoka, MN); Fontaine; Lawrence R. (Minneapolis, MN) |
Assignee: | Unisys Corporation (Blue Bell, PA) |
Appl. No.: | 403622 |
Filed: | September 6, 1989 |
Current U.S. Class: | 713/501; 377/39; 377/52 |
Intern'l Class: | G06F 001/04 |
Field of Search: | 364/200,900 377/39,82 |
4722051 | Jan., 1988 | Chattopadhya | 364/200. |
4831523 | May., 1989 | Lewis et al. | 364/200. |