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United States Patent | 5,010,512 |
Hartstein ,   et al. | April 23, 1991 |
A neural network utilizing the threshold characteristics of a semiconductor device as the various memory elements of the network. Each memory element comprises a complementary pair of MOSFETs in which the threshold voltage is adjusted as a function of the input voltage to the element. The network is able to learn by example using a local learning algorithm. The network includes a series of output amplifiers in which the output is provided by the sum of the outputs of a series of learning elements coupled to the amplifier. The output of each learning element is the difference between the input signal to each learning element and an individual learning threshold at each input. The learning is accomplished by charge trapping in the insulator of each individual input MOSFET pair. The thresholds of each transistor automatically adjust to both the input and output voltages to learn the desired state. After input patterns have been learned by the network, the learning functions is set to zero so that the thresholds remain constant and the network will come to an equilibrium state under the influence of a test input pattern thereby providing, as an output, the learned pattern most closely resembling the test input pattern.
Inventors: | Hartstein; Allan M. (Chappaqua, NY); Koch; Roger H. (Amawalk, NY) |
Assignee: | International Business Machines Corp. (Armonk, NY) |
Appl. No.: | 296111 |
Filed: | January 12, 1989 |
Current U.S. Class: | 706/18; 257/E29.264; 706/25; 706/33; 706/39 |
Intern'l Class: | G06G 007/00; H03K 019/08 |
Field of Search: | 364/807,602,513,131,200 MS File,900 MS File 307/201 |
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