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United States Patent | 5,008,213 |
Kolesar, Jr. | April 16, 1991 |
A wafer scale integration arrangement wherein integrated circuit die of varying size, fabrication processes, and function are commonly mounted in the same host wafer using a filled epoxy material of special characteristics. The mounting epoxy material also serves as a substrate for the die interconnecting conductors in regions adjacent the mounted die. The described assembly also includes a newly available photosensitive polyimide material as a planarization and passivation covering for the die and hose wafer and as a mounting surface for an interconnecting metal conductor array. Multiple levels of interconnection metal. Fabrication processes for the die to host wafer attachment and the passivation covering of the assembly are disclosed.
Inventors: | Kolesar, Jr.; Edward S. (Beavercreek, OH) |
Assignee: | The United States of America as represented by the Secretary of the Air (Washington, DC) |
Appl. No.: | 511475 |
Filed: | April 13, 1990 |
Current U.S. Class: | 438/107; 257/E21.505; 257/E23.004; 257/E23.008; 257/E23.077; 257/E23.119; 438/118; 438/701 |
Intern'l Class: | H01L 021/56; H01L 021/60; H01L 021/82 |
Field of Search: | 437/228,211,225,235,243,915,946,51 |
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